1. Computer Arithmetic, K-maps Prof. Sin-Min Lee Department of Computer Science

3. Bit-Serial and Ripple-Carry Adders Half-adder (HA): Truth table and block diagram Full-adder (FA): Truth table and block diagram

6. Half-Adder Implementations c Three implementations of a half-adder.

8. Full-Adder Implementations

10. Converting whole part w:(105) ten = (?) five Repeatedly divide by fiveQuotientRemainder 1050 211 44 0 Therefore, (105) ten = (410) five Converting fractional part v:(105.486) ten = (410.?) five Repeatedly multiply by fiveWhole PartFraction.486 2.430 2.150 0.750 3.750 Therefore, (105.486) ten  (410.22033) five Radix Conversion: Old-Radix Arithmetic

11. Radix Conversion: New-Radix Arithmetic Converting whole part w: (22033) five = (?) ten ((((2  5) + 2)  5 + 0)  5 + 3)  5 + 3 |-----| : : : : 10 : : : : |-----------| : : : 12 : : : |---------------------| : : 60 : : |-------------------------------| : 303 : |-----------------------------------------| 1518 Converting fractional part v: (410.22033) five = (105.?) ten (0.22033) five  5 5 =(22033) five =(1518) ten 1518 / 5 5 =1518 / 3125 =0.48576 Therefore, (410.22033) five = (105.48576) ten Horner’s rule is also applicable: Proceed from right to left and use division instead of multiplication

12. Horner’s Rule for Fractions Converting fractional part v: (0.22033) five = (?) ten (((((3 / 5) + 3) / 5 + 0) / 5 + 2) / 5 + 2) / 5 |-----| : : : : 0.6 : : : : |-----------| : : : 3.6 : : : |---------------------| : : 0.72 : : |-------------------------------| : 2.144 : |-----------------------------------------| 2.4288 |-----------------------------------------------| 0.48576 Horner’s rule used to convert (0.220 33)five to decimal

13. Signed-Magnitude Representation Four-bit signed-magnitude number representation system for integers

14. Two’s- and 1’s-Complement Numbers Two’s complement = radix complement system for r = 2 M = 2 k 2 k – x = [(2 k – ulp) – x] + ulp = x compl + ulp Range of representable numbers in with k whole bits: from –2 k–1 to 2 k–1 – ulp A 4-bit 2’s-complement number representation system for integers.

15. Why 2’s-Complement Is the Universal Choice Adder/subtractor architecture for 2’s-complement numbers.

16. Signed-Magnitude vs 2’s-Complement Two’s-complement adder/subtractor needs very little hardware other than a simple adder Fig. 2.7 Signed-magnitude adder/subtractor is significantly more complex than a simple adder

17. Truth table to K-Map ABP 001 011 100 111 B A01 011 11 minterms are represented by a 1 in the corresponding location in the K map. The expression is: A.B + A.B + A.B

18. K-Maps Adjacent 1 ’ s can be “ paired off ” Any variable which is both a 1 and a zero in this pairing can be eliminated Pairs may be adjacent horizontally or vertically B A 01 011 11 a pair another pair B is eliminated, leaving A as the term A is eliminated, leaving B as the term The expression becomes A + B

19. Two Variable K-Map A B CP 0000 0010 0101 0110 1001 1010 1101 1110 A.B.C + A.B.C + A.B.C BC A00011110 01 111 One square filled in for each minterm. Notice the code sequence: 00 01 11 10 – a Gray code.

20. Grouping the Pairs BC A 00011110 01 111 equates to B.C as A is eliminated. Here, we can “wrap around” and this pair equates to A.C as B is eliminated. Our truth table simplifies to A.C + B.C as before.

21. Groups of 4 BC A 00011110 011 111 Groups of 4 in a block can be used to eliminate two variables: The solution is B because it is a 1 over the whole block (vertical pairs) = BC + BC = B(C + C) = B.

22. Karnaugh Maps Three Variable K-Map –Extreme ends of same row considered adjacent A BC 00011110 0 1 00 10

23. Karnaugh Maps Three Variable K-Map example A BC 00011110 0 1 X =

24. The Block of 4, again A BC 00011110 0 11 1 11 X = C

25. Returning to our car example, once more Two Variable K-Map A B CP 0000 0010 0101 0110 1001 1010 1101 1110 A.B.C + A.B.C + A.B.C AB C00011110 0111 1 There is more than one way to label the axes of the K-Map, some views lead to groupings which are easier to see.

26. Karnaugh Maps Four Variable K-Map –Four corners adjacent AB CD 00011110 00 01 11 10

27. Karnaugh Maps Four Variable K-Map example AB CD 00011110 00 01 11 10 F =

28. Product-of-Sums We have populated the maps with 1’s using sum-of-products extracted from the truth table. We can equally well work with the 0’s AB C 00011110 0111 11 ABCP 0000 0010 0101 0111 1001 1010 1101 1110 AB C 00011110 00 1000 P = (A + B).(A + C) P = A.B + A.C equivalent

29. Inverted K Maps In some cases a better simplification can be obtained if the inverse of the output is considered –i.e. group the zeros instead of the ones –particularly when the number and patterns of zeros is simpler than the ones

30. Karnaugh Maps Example: Z5 of the Seven Segment Display 0000100001 0001000010 0011000110 0100001000 0101001010 0110101101 0111001110 1000110001 X1X2X3X4Z5 1001010010 1010X1010X 1011X1011X 1100X1101X1110X1111X1100X1101X1110X1111X 01234567890123456789 0010100101 X 1 X 2 X3 X4 00011110 00 01 11 10 Z5 = Better to group 1’s or 0’s?

31. Example: Majority Function Three inputs: A, B, C One output: M Output takes truth value of majority inputs. I.e. –M is 1 iff two of A,B,C is 1 –M is 0 iff two of A, B, C is 0 Notice writing large truth tables is cumbersome

32. Alternative Representation Collect the combinations of variable that give 1 for output. Write the function as a SUM of these terms In terms, write variable name for value 1, and a bar over the name for 0. EG: M = ABC+ABC+ABC+ABC

33. Rationale for New Notation Consider ABC: The product is for AND Consider ABC+ABC: The sum is for OR So we are writing the function as a sum of products I.e. AND-ing OR-terms – Called conjunctive normal form. Consider ABC: This is 1 iff A=0, B=1 and C=1 A function of N variables can be given as sum of 2**N n-variable products

34. Creating Circuits for Boolean Functions M=ABC+ABC+ABC+ABC 1,2,3 are NOT gates feeding lines A,B,C 4,5,6,7 are AND gates corresponding to the four product terms 8 is an OR term corresponding to the sum A,B,C have been inserted to avoid clutter – they could be connected directly out of NOT gate

35. Implementing Boolean Functions Write the truth table Provide inverters for complementing inputs Draw an AND gate for each term with 1in output column Wire the AND gates to appropriate inputs Feed the outputs of all AND gates into an OR gate

36. Using A Single Gate Type It is desirable to use only one type of gate generate the whole circuit. Can use NAND or NOR gate. In order to do so, enough to show that –NOT, AND, OR NAND can be generated by NOR gates –NOT, AND, OR, NOR ca be generated by NAND gates. We say that NAND, NOR are complete for Boolean circuits

37. Completeness of NAND

38. Completeness of NOR

39. Circuit Equivalence Sometimes need to minimize number of elements on a board: –get minimum number of gates –Two input gates instead of four input gates Need to find an equivalent circuit for the given circuit Equivalent= having same input – output behavior = computing same Boolean function Use Boolean Algebra

40. Example: Using AB+AC =A(B+C)

41. Some Laws of Boolean Algebra

42. Consequences of De Morgan ’ s Law

43. Using De Morgan ’ s Laws to covert sum of products to NAND

44. De Morgan again A NAND gate: Y = A.B = A + B is the same as an OR gate with two NOT gates Similarly a NOR gate is the same as an AND gate with two inverters Y = A + B = A.B not the individual terms change the sign not the lot

45. Dual gates not the individual inputs change the gate not the output

46. Truth Tables and Boolean Notation NAND Gate Representation –It is possible to implement any boolean expression using only NAND gates XX NOT AND A B A.B OR A A+B B

47. Truth Tables and Boolean Notation NAND Gate representation –Implement the following circuit using only NAND gates x3 x2 x4 De Morgan can also be represented visually:

48. Exercise Implement NOT, AND and OR using NOR gates Example AND gate dual circuit:

49. Solution Similar pattern to using NAND gates (not surprising) NOT AND OR XX A B A.B A A+B B X X A B A.B A+B A A.B B

50. Truth Tables and Boolean Notation NOR Gate representation –It is also possible to implement any boolean expression using only NOR gates –Implement the following circuit using only NOR gates X4 X3 X2

51. Solution Two NOR gates in sequence acting as NOT ’ s can be eliminated: X4 X3 X2