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FPGA Based System Design

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1 FPGA Based System Design
Lecture 3: Introduction to FPGAs Dr. Nazar Abbas Saqib NUST Institute of Information Technology (NIIT)

2 We will discuss.. Programming Architectures Historical Perpective
PALs, PLDs, CPLDs & FPGAs Pl note source of the figures included in this lecture The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

3 Historical Perspective
First programmable logic devices to appear in 1970 Can implement any set of sum of the product logic equations

4 SRAMs, DRAMs & Microprocessors
Late 1960s and early 1970s – New development in technology Intel introduced first 1024 bit DRAM in 1970 (the 1103) Fairchild introduced first 256-bit static RAM in 1970 (the 4100) Intel also introduced first Microprocessor in 1971 (the 4004) Our intrest: Most of today FPGAs are SRAM based with embedded microprocessors

5 PLD (Programmable Logic Devices)
The first programmable ICs were generally refered to as PLDs They are grouped as SPLDs : Simple PLDs CPLDs: Complex PLDs SPLDs being less sophisticated, less logic The firs programmable chip comes in the form of PROM in 1970s CPLDs being more complex, late 1970s and early 1980s MegaPAL from MMI in 1984

6 PROM (Programmable ROM)
The first simple PLD Prefined AND array, programmable OR array

7 PROM (Programmable ROM)
Programmed PROM Lighter, cheaper, fast logic

8 PLA (Programmable Logic Arrays)
Programmable AND array, programmable OR array

9 PLA (Programmable Logic Arrays)

10 PAL (Programmable Array Logic) GAL (Generic Array Logic)
Exactly opposite to PROM Programmable AND arrays, predefined OR arrays Address speed issues in PLAs

11 CPLDs (Complex PLDs) An array of PLDs Global routing resources
From PLD to other PLDs Example: Cypress 39K

12 ASICs (Application Specific Integerated Circuits)

13 The Gap between PLDs & ASICs
PLDs : Programmable but less complexity ASICs: High complexity but no programmability

14 FPGA Structure CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
Input/Output Block IOB IOB IOB IOB CLB CLB CLB CLB Switch Matrix SM SM SM CLB CLB CLB CLB SM SM SM IOB IOB CLB CLB CLB CLB Configurable Logic Block SM SM SM CLB CLB CLB CLB IOB Typical Capacity : 5 million to 1 billion transistos

15 FPGA Structure Three main components Configurable Logic Blocks (CLB)
Programmable I/Os Programmable Interconnects (Switch Matrix) The CLB is the most important component of FPGA structure

16 Configurable Logic Block (CLB)
2-D array of CLBs Each CLB consists of 2 slices

17 CLB Slice Each slice has 2 logic Cell (LC)
Each Logic cell comprises a LUT, and some additional components i-e Multiplexers, Registers

18 FPGA CLB Slice (Internal View)

19 mux Based CLB (Altera)

20 LUT Based CLB (Xilinx)

21 LUT Based CLB – How to load SRAM cell

22 LUT Based CLB – How to load SRAM cell

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