1. MCS51 - part 2

2. Lecture 2 2/17 MCS51 functioning Clock generator Machine & instruction cycles Paralell ports Reset

3. MCS51 - clocking 3/17 Standard clocking range: 1,2 - 12MHz. Extensions of MCS51 family can be clocked 0Hz - >> 12MHz XTAL2 XTAL1 GND typical circuit external generator XTAL2 XTAL1 GND bufor TTL HMOS external generator XTAL2 XTAL1 GND bufor CMOS CHMOS built-in oscillator XTAL2 XTAL1 GND Φ 1 : 6MHz Φ 2 : 6MHz 12MHz 1 machine cycle

4. 1 machine cycle = 1 instruction cycle Execution of 2, 1-byte instructions, lasting 1 machine cycle each, ex. MOV A,@R1, DEC R2. Codes fetched from external program memory 1 machine cycle = 1 instruction cycle Φ 1 Φ 2 PSEN ALE P0 P2 M, N, O - instruction codes: M=ROM[PC], N=ROM[PC+1], O=ROM[PC+2] MCS51 - machine cycles 4/17

5. 1 machine cycle = 1 instruction cycle Execution of 2, 2-byte instructions, lasting 1 machine cycle each, ex. MOV R3,#5; ADD A,B. Codes fetched from external program memory 1 machine cycle = 1 instruction cycle Φ 1 Φ 2 PSEN ALE P0 P2 MN, OP, Q - instruction codes : M=ROM[PC], N=ROM[PC+1], O=ROM[PC+2], P=ROM[PC+3], Q=ROM[PC+4] MCS51 - machine cycles 5/17

6. 1 machine cycle Execution of 1, 1-byte instruction, lasting 2 machine cycles ex. RET, INC DPTR. Codes fetched from external program memory 1 machine cycle Φ 1 Φ 2 PSEN ALE P0 P2 M, N - instruction codes : M=ROM[PC], N=ROM[PC+1] MCS51 - machine cycles 6/17 1 instruction cycle

7. 1 machine cycle Execution of 1, 2-byte instruction, lasting 2 machine cycles, ex. PUSH B, SJMP label. Codes fetched from external program memory 1 machine cycle Φ 1 Φ 2 PSEN ALE P0 P2 MN, O - instruction codes : M=ROM[PC], N=ROM[PC+1], O=ROM[PC+3] MCS51 - machine cycles 7/17 1 instruction cycle

8. 1 machine cycle Execution of 1, 3-byte instruction, lasting 2 machine cycles, ex. LCALL 23AAh, MOV DPTR,#1. Codes fetched from ext. program memory 1 machine cycle Φ 1 Φ 2 PSEN ALE P0 P2 MNO, P - instruction codes : M=ROM[PC], N=ROM[PC+1], O=ROM[PC+2] P=ROM[PC+3] MCS51 - machine cycles 8/17 1 instruction cycle

9. Execution of 1 instruction reading from external RAM,, ex. MOVX A,@DPTR / MOVX A,@R0 M, N - instruction codes : M=ROM[PC], N=ROM[PC+1] MCS51 - machine cycles 9/17 1 machine cycle Φ 1 Φ 2 PSEN ALE RD P0 P2 1 instruction cycle

10. Execution of 1 instruction writing to external RAM, ex. MOVX @DPTR,A / MOVX @R1,A. M, N - instruction codes: M=ROM[PC], N=ROM[PC+1] MCS51 - machine cycles 10/17 1 machine cycle Φ 1 Φ 2 PSEN ALE WR P0 P2 1 instruction cycle

11. D Q C Q Vcc P0.X external bus/register address & data output reading register internal data bus writing to register reading pin 1010 MCS51 - port P0 11/17 Structure of P0 bit - bidirectional

12. MCS51 - port P2 12/17 Structure of P2 bit - quasi-bidirectional D Q C Q Vcc P2.X external bus/register address output reading register internal data bus writing to register reading pin 1010

13. MCS51 - port P1 13/17 Structure of P1 bit - quasi-bidirectional D Q C Q Vcc P1.X reading register internal data bus writing to register reading pin

14. MCS51 - port P3 14/17 Structure of P3 bit - quasi-bidirectional with alternative function alternative function output reading register internal data bus writing to register reading pin alternative function input D Q C Q Vcc P3.X ! to activate alternative function of any bit, according bit in PX register should be set to „1”

15. MCS51 - port P3 15/17 Alternative functions of P3: P3.0 - RxD - serial input; P3.1 - TxD - serial output; P3.2 - INT0 - external interrupt #0; P3.3 - INT1 - external interrupt #1; P3.4 - T0 - input of pulses counted by timer #0; P3.5 - T1 - input of pulses counted by timer #1; P3.6 - WR - external data memory write strobe; P3.7 - RD - external data memory read strobe. In 80X52 also P1.0 i P1.1 have alternative functions : P1.0 - T2 - input of pulses counted by timer #2; P1.1 - T2EX - gating input for pulses counted by timer #2.

16. MCS51 - ports Px & instructions 16/17 Some instructions are read-modify-write type, i.e. read port register, change it in ALU and write-back to register. There are: ANLPx,arg ORLPx,arg XRLPx,arg JBCPx.bit,adrrel DJNZPx,adrrel CPLPx.bit CLRPx.bit SETPx.bit MOVPx.bit,C INCPx DECPx Instructions reading directly port pins: ANLarg,Px ORLarg,Px XRLarg,Px JBPx.bit,adrrel JNBPx.bit,adrrel CJNEA,Px,adrrel ADDA,Px ADDCA,Px SUBBA,Px MOVarg,Px XCHA,Px PUSHPx

17. MCS51 - reset 17/17 To reset MCU, high level voltage at RESET input should last at least 24 periods of clock. Internal RAM remains unchanged. SFR registers are set as following: PC = 0000hA = 00hTMOD = 00h DPTR = 0000hB = 00hTCON = 00h PSW = 00hP0 = 0FFhTH0 = 00h SP = 07hP1 = 0FFhTL0 = 00h PCON = 00hP2 = 0FFhTH1 = 00h SCON = 00hP3 = 0FFhTL1 = 00h SBUF = ??IP = 00hIE = 00h Vcc RESET GND Vcc RESET GND Vcc