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© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Basic FPGA Architecture FPGA Design Flow Workshop.

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Presentation on theme: "© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Basic FPGA Architecture FPGA Design Flow Workshop."— Presentation transcript:

1 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Basic FPGA Architecture FPGA Design Flow Workshop

2 Basic FPGA Architecture 2 - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Objectives After completing this module, you will be able to: Recognize the basic architectural resources of the Virtex ® -II FPGA List the differences between Virtex-II, Virtex-II Pro™, and Spartan ® -3

3 Basic FPGA Architecture 2 - 4 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview Slice Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

4 Basic FPGA Architecture 2 - 5 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Overview All Xilinx FPGAs contain the same basic resources – Slices contain combinatorial logic and register resources – IOBs interface between the FPGA and the outside world – Programmable interconnect – Other resources Global clock buffers Boundary scan logic

5 Basic FPGA Architecture 2 - 6 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview Slice Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

6 Basic FPGA Architecture 2 - 7 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Slices and CLBs Each Virtex  -II CLB contains four slices – Local routing provides feedback between slices in the same CLB, and it provides routing to neighboring CLBs – A switch matrix provides access to general routing resources CIN Switch Matrix BUFT COUT Slice S0 Slice S1 Local Routing Slice S2 Slice S3 CIN SHIFT

7 Basic FPGA Architecture 2 - 8 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Slice 0 LUT Carry LUT Carry DQ CE PRE CLR D Q CE PRE CLR Simplified Slice Structure Each slice has four outputs – Two registered outputs, two non-registered outputs – Two BUFTs associated with each CLB, accessible by all 16 CLB outputs Carry logic runs vertically, up only – Two independent carry chains per CLB

8 Basic FPGA Architecture 2 - 9 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Detailed Slice Structure The next slides will discuss the slice features – LUTs – MUXF5, MUXF6, MUXF7, MUXF8 (only the F5 and F6 MUX are shown in the diagram) – Carry Logic – MULT_ANDs – Sequential Elements

9 Basic FPGA Architecture 2 - 10 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Combinatorial Logic A B C D Z Look-Up Tables Combinatorial logic is stored in Look-Up Tables (LUTs) – Also called Function Generators (FGs) – Capacity is limited by number of inputs, not complexity Delay through the LUT is constant ABCDZ 00000 00010 00100 00111 01001 01011... 11000 11010 11100 11111

10 Basic FPGA Architecture 2 - 11 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Connecting Look-Up Tables F5 F8 F5 F6 CLB Slice S3 Slice S2 Slice S0 Slice S1 F5 F7 F5 F6 MUXF8 combines the two MUXF7 outputs (from the CLB above or below) MUXF6 combines slices S2 and S3 MUXF7 combines the two MUXF6 outputs MUXF6 combines slices S0 and S1 MUXF5 combines LUTs in each slice

11 Basic FPGA Architecture 2 - 12 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Fast Carry Logic Simple, fast, and complete arithmetic Logic – Dedicated XOR gate for single- level sum completion – Uses dedicated routing resources – All synthesis tools can infer carry logic

12 Basic FPGA Architecture 2 - 13 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only MULT_AND Gate Highly efficient multiply and add implementation – Earlier FPGA architectures require two LUTs per bit to perform the multiplication and addition – The MULT_AND gate enables an area reduction by performing the multiply and the add in one LUT per bit

13 Basic FPGA Architecture 2 - 14 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Flexible Sequential Elements Can be flip-flops or latches Two in each slice; eight in each CLB Inputs can come from LUTs or from an independent CLB input Separate set and reset controls – Can be synchronous or asynchronous All controls are shared within a slice – Control signals can be inverted locally within a slice D CE PRE CLR Q FDCPE D CE S R Q FDRSE D CE PRE CLR Q LDCPE G _1

14 Basic FPGA Architecture 2 - 15 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only LUT Shift Register LUT (SRL16CE) Dynamically addressable serial shift registers – Maximum delay of 16 clock cycles per LUT (128 per CLB) – Cascadable to other LUTs or CLBs for longer shift registers Dedicated connection from Q15 to D input of the next SRL16CE – Shift register length can be changed asynchronously by toggling address A DQ CE DQ DQ DQ LUT D CE CLK A[3:0] Q Q15 (cascade out)

15 Basic FPGA Architecture 2 - 16 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Shift Register LUT Example The SRL can be used to create a No Operation (NOPs) – This example uses 64 LUTs (8 CLBs) to replace 576 flip-flops (72 CLBs) and associated routing and delays 12 Cycles 64 Operation A 4 Cycles8 Cycles Operation B 3 Cycles Operation C 64 12 Cycles Paths are Statically Balanced 9 Cycles Operation D - NOP

16 Basic FPGA Architecture 2 - 17 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview Slice Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

17 Basic FPGA Architecture 2 - 18 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only IOB Element Input path – Two DDR registers Output path – Two DDR registers – Two 3-state enable DDR registers Separate clocks and clock enables for I and O Set and reset signals are shared Reg DDR MUX 3-state OCK1 OCK2 Reg DDR MUX Output OCK1 OCK2 PAD Reg Input ICK1 ICK2 IOB

18 Basic FPGA Architecture 2 - 19 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only SelectIO Standard Allows direct connections to external signals of varied voltages and thresholds – Optimizes the speed/noise tradeoff – Saves having to place interface components onto your board Differential signaling standards – LVDS, BLVDS, ULVDS – LDT – LVPECL Single-ended I/O standards – LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) – PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz) – GTL, GTLP – and more!

19 Basic FPGA Architecture 2 - 20 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Digital Controlled Impedance (DCI) DCI provides – Output drivers that match the impedance of the traces – On-chip termination for receivers and transmitters DCI advantages – Improves signal integrity by eliminating stub reflections – Reduces board routing complexity and component count by eliminating external resistors – Internal feedback circuit eliminates the effects of temperature, voltage, and process variations

20 Basic FPGA Architecture 2 - 21 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview Slice Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

21 Basic FPGA Architecture 2 - 22 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Other Virtex-II Features Distributed RAM and block RAM – Distributed RAMs use the CLB resources (1 LUT = 16 RAM bits) – Block RAMs are dedicated resources on the device (18k bit blocks) Dedicated 18 x 18 multipliers next to block RAMs Clock management resources – Sixteen dedicated global clock multiplexers – Digital Clock Managers (DCMs)

22 Basic FPGA Architecture 2 - 23 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Distributed SelectRAM Resources Uses a LUT in a slice as memory Synchronous write Asynchronous read – Accompanying flip-flops can be used to create synchronous read RAM and ROM are initialized during configuration – Data can be written to RAM after configuration Emulated dual-port RAM – One read/write port – One read-only port RAM16X1S O D WE WCLK A0 A1 A2 A3 LUT RAM32X1S O D WE WCLK A0 A1 A2 A3 A4 RAM16X1D SPO D WE WCLK A0 A1 A2 A3 DPRA0DPO DPRA1 DPRA2 DPRA3 Slice LUT

23 Basic FPGA Architecture 2 - 24 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Block SelectRAM Resources Up to 3.5 Mb of RAM in 18-kb blocks – Synchronous read and write True dual-port memory – Each port has synchronous read and write capability – Different clocks for each port Supports initial values Synchronous reset on output latches Supports parity bits – One parity bit per eight data bits

24 Basic FPGA Architecture 2 - 25 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Dedicated Multiplier Blocks 18-bit twos complement signed operation Optimized to implement multiply and accumulate functions Multipliers are physically located next to block SelectRAM™ memory 18 x 18 Multiplier Output (36 bits) Data_A (18 bits) Data_B (18 bits) 4 x 4 signed 8 x 8 signed 12 x 12 signed 18 x 18 signed

25 Basic FPGA Architecture 2 - 26 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Global Clock Routing Resources Sixteen dedicated global clock multiplexers – Eight on the top-center of the die, eight on the bottom-center – Can be driven by a clock input pad, a Digital Clock Manager (DCM), or local routing Global clock multiplexers provide: – Global clock enable capability (BUFGCE) – Glitch-free switching between clock signals (BUFGMUX) – Traditional clock buffer (BUFG) function Up to eight clock nets can be used in each quadrant of the device

26 Basic FPGA Architecture 2 - 27 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Digital Clock Manager (DCM) Up to twelve DCMs per device – Located on the top and bottom edges of the die – Driven by clock input pads DCMs provide: – Delay-Locked Loop (DLL) – Digital Frequency Synthesizer (DFS) – Digital Phase Shifter (DPS) Up to four outputs of each DCM can drive onto global clock buffers – All DCM outputs can drive general routing

27 Basic FPGA Architecture 2 - 28 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview CLB Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

28 Basic FPGA Architecture 2 - 29 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Spartan-3 versus Virtex-II Lower cost Smaller process = lower core voltage –.09 micron versus.15 micron – Vccint = 1.2V versus 1.5V Different I/O standard support – New standards: 1.2V LVCMOS, 1.8V HSTL and SSTL – Default is LVCMOS, versus LVTTL More I/O pins per package Only half of the slices support RAM or SRL16s (SLICEM) Fewer block RAMs and multiplier blocks – Same size and functionality 8 global clock multiplexers 2 or 4 DCM blocks No internal 3-state buffers – 3-state buffers are in the I/O

29 Basic FPGA Architecture 2 - 30 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only SLICEM and SLICEL Each Spartan™-3 CLB contains four slices – Similar to Virtex™-II Slices are grouped in pairs – Left-hand SLICEM (Memory) LUTs can be configured as memory or SRL16 – Right-hand SLICEL (Logic) LUT can be used as logic only CIN Switch Matrix COUT Slice X0Y0 Slice X0Y1 Fast Connects Slice X1Y0 Slice X1Y1 CIN SHIFTIN Left-Hand SLICEM Right-Hand SLICEL SHIFTOUT

30 Basic FPGA Architecture 2 - 31 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview CLB Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

31 Basic FPGA Architecture 2 - 32 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Virtex-II Pro Features 0.13 micron process Up to 24 RocketIO™ Multi-Gigabit Transceiver (MGT) blocks – Serializer and deserializer (SERDES) – Fibre Channel, Gigabit Ethernet, XAUI, Infiniband compliant transceivers,…and others – 8-, 16-, and 32-bit selectable FPGA interface – 8B/10B encoder and decoder Up to four PowerPC RISC processor blocks – Thirty-two 32-bit General Purpose Registers (GPRs) – Low power consumption: 0.9mW/MHz – IBM CoreConnect  bus architecture support Xilinx: Editor: Check if CoreConnect is an IBM trademark Xilinx: Editor: Check if CoreConnect is an IBM trademark

32 Basic FPGA Architecture 2 - 33 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview CLB Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

33 Basic FPGA Architecture 2 - 34 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Skills Check

34 Basic FPGA Architecture 2 - 35 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Review Questions List the primary slice features List the three ways a LUT can be configured

35 Basic FPGA Architecture 2 - 36 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Answers List the primary slice features – Look-up tables and function generators (two per slice, eight per CLB) – Registers (two per slice, eight per CLB) – Dedicated multiplexers (MUXF5, MUXF6, MUXF7, MUXF8) – Carry logic – MULT_AND gate List the three ways a LUT can be configured – Combinatorial logic – Shift register (SRL16CE) – Distributed memory

36 Basic FPGA Architecture 2 - 37 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Summary Slices contain LUTs, registers, and carry logic – LUTs are connected with dedicated multiplexers and carry logic – LUTs can be configured as shift registers or memory IOBs contain DDR registers SelectIO™ standards and DCI enable direct connection to multiple I/O standards while reducing component count Virtex™-II memory resources include: – Distributed SelectRAM™ resources and distributed SelectROM (uses CLB LUTs) – 18-kb block SelectRAM resources

37 Basic FPGA Architecture 2 - 38 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Summary Virtex™-II contains dedicated 18 x 18 multipliers next to each block SelectRAM™ resource Digital Clock Managers provide: – Delay-Locked Loop (DLL) – Digital Frequency Synthesizer (DFS) – Digital Phase Shifter (DPS)

38 Basic FPGA Architecture 2 - 39 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Where Can I Learn More? User Guides – http://support.xilinx.com  Documentation Application Notes – http://support.xilinx.com  Documentation  App Notes

39 Basic FPGA Architecture 2 - 40 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Overview CLB Resources I/O Resources Other Virtex-II Features Spartan-3 versus Virtex-II Virtex-II Pro Features Summary Appendix

40 Basic FPGA Architecture 2 - 41 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Virtex-II Architecture Virtex™-II architecture’s core voltage operates at 1.5V I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) Clock Management (DCMs, BUFGMUXes) Block SelectRAM™ resource Dedicated multipliers Programmable interconnect

41 Basic FPGA Architecture 2 - 42 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Double Data Rate Registers DDR registers can be clocked by – Clock and NOT(Clock) if the duty cycle is 50/50 – The outputs CLK0 and CLK180 of a DCM If D1 = “1” and D2 = “0”, the output is a copy of Clock – Use this technique to generate a clock output that is synchronized to DDR output data Reg DDR mux FDDR OCK1 OCK2 D1 D2 PAD OBUFClock

42 Basic FPGA Architecture 2 - 43 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only ConfigurationDepthData BitsParity Bits 16k x 116 kb10 8k x 28 kb20 4k x 44 kb40 2k x 92 kb81 1k x 181 kb162 512 x 36512324 Dual-Port Block RAM Configurations Configurations available on each port Independent configurations on ports A and B – Supports data width conversion, including parity bits Port A: 8-b IN 8-bit OUT 32-bit Port B: 32-b

43 Basic FPGA Architecture 2 - 44 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Clock Buffer Configurations Clock Buffer (BUFG) – Low-skew clock distribution Clock Enable Buffer (BUFGCE) – Holds the clock output low when CE is inactive – CE can be active-High or active-Low – Changes in CE are only recognized when the clock input is low to avoid glitches and short clock pulses OI CE BUFGCE OI BUFG

44 Basic FPGA Architecture 2 - 45 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Clock Buffer Configurations Clock Multiplexer (BUFGMUX) – Switches glitch-free from one clock to another – After a change on S, the BUFGMUX waits for the currently selected clock input to go Low – The output is held Low until the newly selected clock goes Low, then switches BUFGMUX O I1 I0 S I1 S O Wait for low Switch

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