1. VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture notes

2. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Wire and via structures. n Wire parasitics. n Transistor parasitics. n Fabrication theory and practice.

3. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Wires and vias p-tub poly n+ metal 1 metal 3 metal 2 vias

4. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Metal interconnect n Many layers of metal interconnect are possible. –12 layers of metal are common. n Lower layers have smaller features, higher layers have larger features. n Can’t directly go from a layer to any other layer.

5. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Copper interconnect n Much better electrical characteristics. n Copper is poisonous to semiconductors--- must be isolated from silicon. –Bottom layer of interconnect is aluminum.

6. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Metal migration n Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. n Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

7. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Metal migration problems and solutions n Marginal wires will fail after a small operating period—infant mortality. n Normal wires must be sized to accomodate maximum current flow: I max = 1.5 mA/  m of metal width. n Mainly applies to V DD /V SS lines.

8. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Diffusion wire capacitance n Capacitances formed by p-n junctions: n+ (N D ) depletion region substrate (N A ) bottomwall capacitance sidewall capacitances

9. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Depletion region capacitance n Zero-bias depletion capacitance: –C j0 =  si /x d. n Depletion region width: –x d0 = sqrt[(1/N A + 1/N D )2  si V bi /q]. n Junction capacitance is function of voltage across junction: –C j (V r ) = C j0 /sqrt(1 + V r /V bi )

10. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Poly/metal wire capacitance n Two components: –parallel plate; –fringe. plate fringe

11. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Metal coupling capacitances n Can couple to adjacent wires on same layer, wires on above/below layers: metal 2 metal 1

12. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Example: parasitic capacitance measurement n n-diffusion: bottomwall=2 fF, sidewall=2 fF. n metal: plate=0.15 fF, fringe=0.72 fF. 3  m 0.75  m 1  m 1.5  m 2.5  m

13. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Wire resistance n Resistance of any size square is constant:

14. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Skin effect n At low frequencies, most of copper conductor’s cross section carries current. n As frequency increases, current moves to skin of conductor. –Back EMF induces counter-current in body of conductor. n Skin effect most important at gigahertz frequencies.

15. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Skin effect, cont’d n Isolated conductor: n Conductor and ground: Low frequency High frequency Low frequency High frequency

16. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Skin depth n Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: –  = 1/sqrt(  f  ) –f = signal frequency –  = magnetic permeability –  = wire conducitvity

17. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Effect on resistance n Low frequency resistance of wire: –R dc = 1/  wt n High frequency resistance with skin effect: –R hf = 1/2  (w + t) n Resistance per unit length: –R ac = sqrt(R dc 2 +  R hf  2  Typically  = 1.2.

18. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Transistor gate parasitics n Gate-source/drain overlap capacitance: gate sourcedrain overlap

19. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Transistor source/drain parasitics n Source/drain have significant capacitance, resistance. n Measured same way as for wires. n Source/drain R, C may be included in Spice model rather than as separate parasitics.

20. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Why we need design rules n Masks are tooling for manufacturing. n Manufacturing processes have inherent limitations in accuracy. n Design rules specify geometry of masks which will provide reasonable yields. n Design rules are determined by experience.

21. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Design rules and yield n Design rules are determined by manufacturing process characteristics. n Design rules should provide adequate yield if followed. n Types of design rules: –Spacing. –Separation. –Composition.

22. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Yield n Gamma distribution for yield of a single type of structure: –Y i = [1/(1+A  i )]  i. n Total yield for the process is the product of all yield components: –Y =  Y i.

23. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Manufacturing problems n Photoresist shrinkage, tearing. n Variations in material deposition. n Variations in temperature. n Variations in oxide thickness. n Impurities. n Variations between lots. n Variations across a wafer.

24. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Transistor problems n Varaiations in threshold voltage: –oxide thickness; –ion implanatation; –poly variations. n Changes in source/drain diffusion overlap. n Variations in substrate.

25. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Wiring problems n Diffusion: changes in doping -> variations in resistance, capacitance. n Poly, metal: variations in height, width -> variations in resistance, capacitance. n Shorts and opens:

26. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Oxide problems n Variations in height. n Lack of planarity -> step coverage. metal 1 metal 2

27. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Via problems n Via may not be cut all the way through. n Undesize via has too much resistance. n Via may be too large and create short.

28. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Scaling theory n Chips get better as features shrink in classical scaling theory: –Capacitive load goes down faster than current. n Classical scaling theory runs into complications at nanometer features. –Leakage. –Smaller supply voltage.

29. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Scaling model  /x. W  W/x, L  L/x. t ox  t ox /x. N d  N d /x. V DD  V SS  (V DD  V SS )/x.

30. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Current and capacitance scaling n Saturation drain current scales as 1/x. n Capacitance scales as 1/x. n Total performance over scaling: –[C’V’/l’]/[CV/l] = 1/x. –Circuit speeds up by factor x.

31. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Interconnect scaling n Two varieties of interconnect scaling: –Ideal scaling reduces vertical and horizontal dimensions equally. –Constant dimension does not change wiring sizes. –Higher levels of interconnect are constant dimension---same as older technologies.

32. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Interconnect scaling trends Ideal scalingConstant dimension Line width/spacingS1 Wire thicknessS1 Interlevel dielectricS1 Wire length1/sqrt(S) Resistance/unit length1/S 2 1 Capacitance/unit length11 RC delay1/S 3 1/S Current density1/SS

33. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR ITRS roadmap n Semiconductor industry projects fabrication trends. –Helps plan future technologies. n Roadmap describes features, technology required to get to those goals.

34. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR ITRS roadmap 2005-2012 20052006200720082009201020112012 CPU metal pitch 9075685952454036 CPU gate length 3228252320181614 ASIC gate length 4538322825232018