1. Session 5: Projects 1

2. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

3. RLC extraction : 3 Inductance Modeling Reducing Capacitance Skin Effect / Anomalous Skin Effect

4. Interconnect Delay : 4 High Speed Global On-Chip Interconnects Compact Model for Delay Near Speed-of-Light On-Chip Electrical Interconnects Moment-Matching Technique

5. Interconnect Noise : 5 Moment-Matching Technique

6. Repeater Insertion: 6

7. Bit Rate Limitation : 7 Data Integrity : maximum data transfer rate. Digital communication Throughput-Centric Wave-Pipelined Interconnect

8. Process Variations : 8

9. Power Dissipation : 9

10. Clock Distribution : 10

11. 3D Integration: 11 Electrical modeling of Interconnects in 3-D ICs

12. Speed/Power/Area Tradeoffs : 12

13. Power Distribution / Electromigration : 13 Design / Analysis / Optimization of power distribution network Local power distribution network Global power distribution network

14. Impact of Cu vs. Al Metallization on Performance : 14

15. Thermal Modeling of Metallic Interconnects : 15

16. CNTs as Interconnect: 16 PERFORMANCE COMPARISON BETWEEN COPPER, CARBON NANOTUBE, AND OPTICS FOR OFF-CHIP AND ON-CHIP INTERCONNECTS

17. Optical Interconnects : 17