1. 3/4/20031 ECE 551: Digital System Design * & Synthesis Lecture Set 3 3.1: Verilog - User-Defined Primitives (UDPs) (In separate file) 3.2: Verilog – Operators, Continuous Assignments, Behavioral Modeling, Procedural Assignments, Flip-Flop and Latch Models

2. 3/4/20032 Summary of Verilog Operators - 1 TypeArgument(s)ResultOperatorsExample Arithmetic2 operandsBinary Word +, -, *, /, %C = A + B; Bitwise2 operandsBinary Word ~, &, |, ^, ~ ^C = A ^ B; Reduction1 operandBit&, ~&, |, ~|, ^, ~ ^ c = &A[7:0]; Logical2 operandsBoolean!, &&, ||, = =, !=, = = =, != = if (a && b) then  Valid operations and result type depend on types of input operands.

3. 3/4/20033 Summary of Verilog Operators - 2 *  Valid operations and result type depend on types of input operands. TypeArgument(s)ResultOperatorsExample Relational2 operandsBoolean, >=if (A <= B) then Shift - Logical Shift-Arithmetic 1 or 2 operands Binary Word >, >> C = A << 4; Conditional3 operandsExpression? :(A < B) ? A: B; Concatenation, Replication 2 or more operands Binary Word {},{{}}C = {A, B}; C = {2{A}};

4. Operator Precedence + - ! ~ (unary) ** * / % + - (binary) > >> >= = = != = & ~& ^ ^~ ~^ | ~| && || ? : Highest Lowest  Operators in same box have the same precedence

5. 3/4/20035 In-class Operator Discussion  Bitwise and (&) and logical and (&&)  Reduction and (&) and nand(~&)  Logical equality(==)/inequality(!=)  Case equality (===)/inequality(!==)  Right shift (>>) and Arithmetic right shift (>>>)

6. 3/4/20036 Special Registers: Memories and Strings  A memory is an array of n-bit registers  reg [15:0] mem_name [0:127]; //128 16-bit words  Reference can only be made to a word of memory mem_name[122] = -127;// assigns word  mem_name[13][5] = 1;// illegal  Verilog 2001 allows multidimensional arrays/memories  Strings are stored using properly-sized registers  reg [12*8: 1]stringvar;// 12 character string  stringvar = “Hello World”;// string assignment  Unused characters are filled with zeros

7. 3/4/20037 Types of Assignments  Continuous  Procedural  Blocking  Non-Blocking  Continuous assign, deassign force, release

8. 3/4/20038 Continuous Assignment  Assigns values to nets, bits of nets, parts of nets, or concatenation of any of the above  Appear in RTL/dataflow descriptions  Syntax assign LHS = RHS  Execution: If operand on RHS changes, RHS evaluated and if RHS value changes, new value assigned to LHS

9. 3/4/20039 Continuous Assignment Examples  assign S = A + B;  assign {C0, S} = A + B + CI;  assign W = X & (Y ^ Z);  assign p = (m >= n) ? m : n;  assign x = y | z;

10. 3/4/200310 Procedural Assignments  Types  assign = continuous assignment  = blocking assignment  <= non-blocking assignment  Assignments (with one exception) to:  reg  integer  real  realtime  time

11. 3/4/200311 Procedural Assignments - Some Rules  Variable can be referenced anywhere in module  Variable can be assigned only with procedural statement, task or function  Variable cannot be input or inout  Net can be referenced anywhere in module  Net may not be assigned within behavior, task or function. Exception: force … release  Net within a module must be driven by primitive, continuous assignment, force … release or module port

12. 3/4/200312 Procedural Continuous Assignment  Two types  assign … deassign to variable dynamic binding to target variable  force … release to variable or net dynamic binding to target variable or net

13. 3/4/200313 Procedural Continuous Assignment - Examples  Example 1: reg Q; always @ (clk) if clk = 1 assign Q = D; else assign Q = Q;  Example 2: net Q; always @ (set or reset) if set = 1 force Q = 1; else if reset = 1 force Q = 0; else Q = Q;

14. 3/4/200314 Procedural Continuous Assignment  A procedural continuous assignment overrides all regular procedural assignments to variables  Example: module dff_pc (q, d, clear, preset, clk); output q; input d, clear, preset clk; reg q; //continued on next slide

15. 3/4/200315 Procedural Continuous Assignment always@(clear or preset) if (!clear) assign q = 0; else if (!preset) assign q = 1; else deassign q; always@(posedge clk) q = d; endmodule

16. 3/4/200316 Behavioral Constructs  Concurrent communicating behaviors => processes = behaviors  Two constructs  Initial - one-time sequential activity flow - not synthesizable but good for testbenches  Always - cyclic (repetitive) sequential activity flow  Use procedural statements that assign only variables (with exception of force/release on net)

17. 3/4/200317 Behavioral Constructs (continued)  Continuous assignments and primitives assign outputs whenever there are events on the inputs  Behaviors assign values when an assignment statement in the activity flow executes. Input events on the RHS do not initiate activity - control must be passed to the statement.

18. 3/4/200318 Behavioral Constructs (continued)  Body may consist of a single statement or a block statement  Block statement begins with begin and ends with end  Statements within a block execute sequentially  Behaviors are an elaborate form of continuous assignments or primitives but operate on registers (with one exception) rather than nets

19. 3/4/200319 Behavioral Constructs - Example  Initial:  Always: initial always begin begin one = 1;F1 = 0, F2 = 0 two = one + 1;# 2 F1 = 1; three = two + 1;# 4 F2 = 1; four = three + 1;# 2 F1 = 0; five = four + 1;# 4; end

20. 3/4/200320 Procedural Timing, Controls & Synchronization  Mechanisms  Delay Control Operator (#)  Event Control Operator (@)  Event or  Named Events  wait construct

21. 3/4/200321 Procedural Timing, Controls & Synchronization  Delay Control Operator (#)  Precedes assignment statement - postpones execution of statement  For blocking assignment (=), delays all statements that follow it  Blocking assignment statement must execute before subsequent statements can execute.  Example: always @(posedge clk), #10 Q = D;

22. 3/4/200322 Procedural Timing, Controls & Synchronization  Event Control Operator (@)  Synchronizes the activity flow of a behavior to an event (change) in a register or net variable or expression  Example 1: @(start) RegA = Data;  Example 2: @(toggle) begin … @ (posedge clk) Q = D; … end

23. 3/4/200323 Procedural Timing, Controls & Synchronization  Event or - allows formation of event expression  In Verilog 2001 can use, instead of or  Example: always @ (X1 or X2 or X3) assign Y = X1 & X2 | ~ X3;

24. 3/4/200324 Procedural Timing, Controls & Synchronization  Meaning of posedge: 0 -> 1, 0 -> x, x -> 1  Special Example: always @ (set or reset or posedge clk) begin if (reset == 1) Q = 0; else if (set = = 1) Q = 1; else if (clk == 1) Q = data; end // Does this work correctly? Why or why not?

25. 3/4/200325 Procedural Timing, Controls & Synchronization  Named Events module cpu (…); always @ (peripheral.interrupt) begin... end module peripheral (…); event interrupt; … -> interrupt;

26. 3/4/200326 Procedural Timing, Controls & Synchronization  wait Construct  Suspends activity in behavior until expression following wait is TRUE  Example: always begin a = b; c = d; wait (advance); end

27. 3/4/200327 Latches and Flip-Flops  D-Latch  PET D Flip-Flop with Asynchronous Set and Reset  PET D Flip-Flop with Synchronous Set and Reset

28. 3/4/200328 Verilog Model of D-Latch * module d_latch (enable,d, q); input enable, d; output q; reg q; always @(enable or d) if (enable) q <= d; endmodule

29. 3/4/200329 Verilog Model of PET DFF with Asynchronous Set and Reset module pet_dff_sr (clk, d, reset, set, q); input clk, d, reset, set; output q; reg q; always @(posedge clk or negedge reset or negedge set) //active low R and S if (!reset) q <= 0; else (!set) q <= 1; else q <= d; endmodule

30. 3/4/200330 Verilog Model of PET DFF with Synchronous Set and Reset module pet_dff_ssr (clk, d, reset, set, q); input clk, d, reset, set; output q; reg q; always @(posedge clk) //active low reset and set if (!reset) q <= 0; else (!set) q <= 1; else q <= d; endmodule

31. 3/4/200331 Things To Know  Operators  Interaction of Operators and Operands  Widths  For x and z values  Assignments  Continuous  Procedural  Behaviors  Behavior Controls  Verilog coding for simple storage elements