1. Device models
Mohammad Sharifkhani

2. A model for manual analysis

3. Current-Voltage Relations The Deep-Submicron Era-4 V DS
(V)
0.5 1
1.5 2
2.5
x 10 I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
Linear
Relationship

4. Velocity Saturation u ( m / s ) u = 10 x = 1.5 x (V/µm) 5 sat n c
Constant velocity
Constant mobility (slope = µ) x c
= 1.5 x
(V/µm)

5. Perspective I V Long-channel device V = V Short-channel device V V - VGS DD
Short-channel device V V
- V V
DSAT GS T DS

6. ID versus VGS linear quadratic quadratic Long Channel Short Channel
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V GS
(V) I D
(A)
0.5 1
1.5 2
2.5
x 10 -4 V GS
(V) I D
(A)
linear
quadratic
quadratic
Long Channel
Short Channel

7. ID versus VDS Resistive Saturation VDS = VGS - VT Long Channel
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V DS
(V) I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive
Saturation
VDS = VGS - VT -4 V DS
(V)
0.5 1
1.5 2
2.5
x 10 I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Long Channel
Short Channel

8. Unified model

9. Unified model
Model presented is compact and suitable for hand analysis.
Still have to keep in mind the main approximation: that VDSat is constant .
When is it going to cause largest errors?
When E scales – transistor stacks.
But the model still works fairly well.

10. Velocity saturation

11. Velocity saturation
Smaller EcL  Smaller VDsat  Saturates quicker

12. Velocity saturation

13. Velocity saturation

14. Velocity saturation

15. Velocity Saturation

16. Output resistance Slope in I-V characteristics caused by:
Channel length modulation
Drain-induced barrier lowering (DIBL)
Both effects increase the saturation current beyond the saturation point
The simulations show approximately linear dependence of Ids on Vds in saturation.

17. Output resistance

18. Output resistance

19. Output resistance

20. Transistor stacks

21. Transistor stacks (Velocity sat.)
NAND Suffers less from VS
In NAND VDsat is larger

22. Velocity Saturation How about NAND3? How about PMOS networks?
IDSat = 1/2 of inverter IDSat (instead of 1/3)
How about PMOS networks?
NOR2 – 1.8x, NOR3 – 2.4x, NOR x
What is ECL for PMOS?

23. Alpha power law

24. Alpha power law This is not a physical model Simply empirical:
Can fit (in minimum mean squares sense) to variety of α’s, VTh
Need to find one with minimum square error – fitted VTh
can be different from physical
Can also fit to α = 1
What is VTh?

25. Alpha power law

26. I-V Curves
Triode
Vel. Sat.
Regular sat.

27. I-V curves

28. A PMOS Transistor Assume all variables negative! -2.5 -2 -1.5 -1 -0.5
-0.8
-0.6
-0.4
-0.2
x 10 -4 V DS
(V) I D
(A)
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Assume all variables
negative!
VGS = -2.5V

29. Transistor Model for Manual Analysis

30. The Transistor as a Switch

31. The Transistor as a Switch

32. The Transistor as a Switch

33. MOS capacitance
The capacitance of the MOS affects the dynamic behavior of a circuit
Speed Caps
Proper modeling is needed

34. MOS Capacitance

35. Dynamic Behavior of MOS Transistor

36. The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlapd L
Polysilicon gate
Top view
Gate-bulk
overlap
Source n +
Drain W t ox n +
Cross section L
Gate oxide

37. Gate Cap

38. Gate Capacitance
Cut-off
Resistive
Saturation
Most important regions in digital design: saturation and cut-off

39. Diffusion Capacitance
Channel-stop implant N 1 A
Side wall
Source W N D
Bottom x
Side wall j
Channel L S
Substrate N A

40. Junction Capacitance

41. Capacitances in 0.25 mm CMOS process

42. MOS Caps behavior