1. Computer Arithmetic See Stallings Chapter 9 Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

2. Arithmetic & Logic Unit (ALU)
ALU does the calculations
“Everything else in the computer is there to service this unit” (!)
Handles integers
May handle floating point (real) numbers
there may be a separate floating point unit (FPU) (“math co-processor”)
or an on-chip separate FPU (486DX +)
on Pentium (earlier slides) multiple ALUs and FPUs
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

3. requested arithmetic operation
ALU Inputs and Outputs
requested arithmetic operation
Status e.g overflow?
operands (in)
operands (out)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

4. Integer Representation
Positive numbers stored in binary
e.g. 41=
Only have 0 & 1 to represent everything
No minus sign!
No period!
Exponent?
Two approaches to integers
Sign-Magnitude
Twos complement
unsigned
integers?
“counting
numbers”?
Is zero
positive?
(NO!)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

5. Sign-Magnitude Approach
Leftmost bit is most
significant bit (msb)
Rightmost bit is least
significant bit (lsb)
Left most bit is sign bit
0 means positive
1 means negative
+18 =
-18 =
Problems!!
Need to consider both sign and magnitude in arithmetic
Two representations of zero (+0 and -0)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

6. Two’s Complement +3 = 00000011 +2 = 00000010 subtract 1 +1 = 00000001
+0 =
-1 =
-2 =
-3 =
subtract 1
subtract 1 ???? add 1
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

7. Aside re Binary Arithmetic
You should already know that
02+12 = 12
= 102 (or = 02 carry 1)
= 002 carry 1
12 – 12 = 02 (no borrow), 02 – 12 = 12 borrow 1
– 12 = borrow 1
= 0•24 + 0•23 + 0•22 + 1•21 + 1•20 =  bi 2i
K bit binary
number,
e.g. K = 5
K-1
i=0 b2
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

8. Two’s Complement Benefits
One representation of zero
Arithmetic works easily (see later)
Negating is fairly easy:
310 =
bitwise complement gives
Add = –310
two’s complement
one’s complement
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

9. Two’s Complement Benefits
What about negating a negative number ?
– 310 =
bitwise complement gives
Add = 310
GOOD! – ( – 3 ) = 3
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

10. Two’s Complement Integers
In n bits, can
store integers from
–2n-1 to + 2n-1 – 1
neg
pos
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

11. Range of Numbers Largest positive Smallest (?) negative
8 bit 2s complement
+127 = = 27 -1
-128 = = -27
16 bit 2s complement
= =
= = -215
N bit 2s complement
= 2N-1 - 1
= -2N-1
Largest positive
Smallest (?) negative
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

12. Negation Special Case 1 0 = 00000000 Bitwise not 11111111 Add 1 +1
0 =
Bitwise not
Add
Result
if this bit is ignored:
– 0 = 0
hmmm . . . OK
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

13. Carry vs. Overflow
So what about the ignored bit on the last slide?
CARRY: is an artifact of performing addition
always happens: for binary values, carry = 0 or 1
exists independently of computers!
OVERFLOW: an exception condition that results from using computers to perform operations
caused by restricting values to fixed number of bits
occurs when result exceeds range for the number of bits
important limitation of using computers!
e.g. Y2K bug!
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

14. Overflow is Implementation Dependent!
recall example: negation of 0
binary addition is performed – regardless of interpretation +1
for this addition
the answer is:
with carry = 1
fixed number
of bits to
represent
values
carry
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

15. Unsigned Interpretation  Overflow
consider values as unsigned integers +1
but = 256 ??
answer = 0 ???
OVERFLOW occurred!
WHY? cannot represent 256 as an 8-bit unsigned integer!
25510
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

16. Signed Interpretation  No Overflow
consider values as signed integers +1
–1 + 1 = 0
answer is correct!
OVERFLOW did not occur (even though carry =1!)
WHY? can represent 0 as an 8-bit signed integer!
– 110
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

17. what about negating zero?
Negation Special Case 2
– 128 =
bitwise not
Add 1 to lsb
Result
Whoops!
– (– 128) = – 128
Need to monitor msb (sign bit)
It should change during negation?
Problem! OVERFLOW!
what about negating zero?
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

18. Conversion Between Lengths, e.g. 8  16
Positive number: add leading zeros
+18 =
+18 =
Negative numbers: add leading ones
-18 =
-18 =
i.e. pack with msb (sign bit)
called “sign
extension”
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

19. Addition and Subtraction
a – b = ?
Normal binary addition
Monitor sign bit of result for overflow
Take twos complement of b and add to a
i.e. a – b = a + (– b)
So we only need addition and 2’s complement circuits
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

20. Hardware for Addition and Subtraction
A – B = ? CF
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

21. SYSC 5704: Elements of Computer Systems
Adders
Murdocca, Figure 3-2
Ripple-Carry Adder
Murdocca, Figure 3-6
Addition/Subtraction Unit
Fall 2008
SYSC 5704: Elements of Computer Systems

22. Multiplication Complicated Work out partial product for each digit
Take care with place value (column)
Add partial products
Aside: Multiply by 2? (shift?)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

23. Multiplication Example
Multiplicand (1110)
x Multiplier (1310)
Partial products
Note: if multiplier bit is 1
copy multiplicand (place value)
otherwise zero
Product (14310)
Note: need double length result – could easily overflow single word
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

24. Unsigned Binary Multiplication
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

25. Execution of 4-Bit Example M x Q = A,Q
1 add
0 no add
1 add
1 add
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

26. Flowchart for Unsigned Binary Multiplication
number of bits
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

27. SYSC 5704: Elements of Computer Systems
Array Multiplier
Murdocca,
Figure 3-23
The serial method we used for multiplying two unsigned integers in Section requires only a small amount of hardware, but the time required to multiply two numbers of length w grows as w2. We can speed the multiplication process so that it completes in just 2wsteps by implementing the manual process shown in Figure 3-10 in parallel. The general idea is to form a one-bit product between each multiplier bit and each multiplicand bit, and then sum each row of partial product elements from the top to the bottom in systolic (row by row) fashion.
The structure of a systolic array multiplier is shown in Figure A partial product (PP) element is shown at the bottom of the figure. A multiplicand bit (mi) and a multiplier bit (qj) are multiplied by the AND gate, which forms a partial product at position (i, j) in the array. This partial product is added to the partial product from the previous stage (bj) and any carry that is generated in the previous stage (aj). The result has a width of 2w and appears at the bottom of the array (the high-order wbits) and at the right of the array (the low-order w bits).
Fall 2008
SYSC 5704: Elements of Computer Systems

28. Multiplying Negative Numbers
Multiplying negative numbers by this method does not work!
Solution 1
Convert to positive if required
Multiply as above
If signs were different, negate answer
Solution 2
Booth’s algorithm – not in scope of course? (Page 322)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

29. Computer Architecture: Arithmetic
Booth’s Algorithm : Increase speed of a multiplication when there are consecutive ones or zeros in the multiplier.
Based on shifting of multiplier from right-to-left
If at boundary of a string of 0’s, add multiplicand to product (in proper column)
If at boundary of a string of 1’s, subtract multiplicand to product (in proper column)
If within string, just shift.
The computer architecture shown so far is simple and straightforward. But there are considerable study areas in the field of computer architecture as it pertains to computer arithmetic. New algorithms, new hardware implementations for fast addition, subtraction, multiplication and division as well as FPP are under work.
Fast carry look ahead
Residue Arithmetic
Booth’s algorithm:
The book shows the weakness of this algorithm (if the multiplier is made up of alternating bits, you end up adding and subtracting more than in the simplifier version)
The book then shows the modified.
Fall 2008
SYSC 5704: Elements of Computer Systems

30. Booth’s Algorithm

31. Example of Booth’s Algorithm

32. Murdocca Example: Booth
Figure 3-19
(21)
(14)
(1st transition)
So the number of additions is reduced.
Why do we subtract ? = – … So we add a bigger number and subtract the extra. But we do it in the opposite order because we are scanning from right to left.
The text has further modifications of the Booth algorithm (which further reduces the number of additions) as well as an array multiplier (which uses parallelism in order to reduce the impact of wider buses). You are left to consider these yourselves.
Fall 2008
SYSC 5704: Elements of Computer Systems

33. Division More complex than multiplication
Negative numbers are really bad!
Based on long division
Aside: Divide by 2? (shift?)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

34. Division of Unsigned Binary Integers
Quotient
Divisor
1011
Dividend
1011
001110
Partial
Remainders
1011
001111
1011
Remainder
100
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

35. Flowchart for Unsigned Binary Division
Divisor
Flowchart for Unsigned Binary Division
Subtract
Shift left
Quotient
Remainder
/ Dividend
differences with multiply?
shift left
subtract?
no “C”
add
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

36. SYSC 5704: Elements of Computer Systems
Division is somewhat more complex than multiplication; based on the same general principles
Fall 2008
SYSC 5704: Elements of Computer Systems

37. Real Numbers Numbers with fractions Could be done in pure binary
= =
Where is the binary point?
Fixed?
Very limited representation ability
Moving?
How do you show where it is?
fixed point
floating point
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

38. Normalization Floating Point (FP) numbers are usually normalized
i.e. exponent is adjusted so that leading bit (msb) of significand is always 1
Since msb is always 1 there is no need to store it
Recall scientific notation where numbers are normalized to give a single digit before the decimal point
e.g x 103
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

39. Floating Point (Scientific Notation)
(Biased)
exponent
Sign bit
(stored) significand
+/ – 1.significand x 2exponent
Floating point misnomer: Point is actually fixed after first digit of the significand: xxxxxx
xxxxxx is stored signficand
Exponent indicates place value (point position)
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

40. Floating Point Examples
Typo here!
What's wrong?
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

41. Signs for Floating Point
Significand: explicit sign bit (msb)
rest of bits are magnitude (sort of)
Exponent is in excess or biased notation
8 bit exponent field
binary value range 0-255
Excess (bias) 127 means
Subtract 127 to get correct value
Range -127 to +128
for k bit exponent:
bias = 2k–1 –1
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

42. FP Ranges Range: The range of numbers that can be represented
For a 32 bit number
8 bit exponent
+/  +/- 1.5 x 1038
Accuracy: The effect of changing lsb of significand
23 bit significand 2-23  1.2 x 10-7
About 6 decimal places
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

43. Expressible Numbers 2 2
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

44. IEEE 754 Standard for floating point storage 32 and 64 bit standards
8 and 11 bit exponent respectively
Extended formats (both significand and exponent) for intermediate results
special cases: (table 9.4, page 318)
0 (how to normalize?)
denormalized (for arithmetic)
 (how to quantify?)
Not a number (NaN  exception)
How?
use exponent = all 0’s
 zero, denormalized
use exponent = all 1’s
infinity, NAN
reduces range!
2 –126 to 2127
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

45. IEEE 754 Formats
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

46. FP Arithmetic +/- Check for zeros
Align significands (adjusting exponents)
 denormalize!
Add or subtract significands
Normalize result
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

47. FP Addition & Subtraction Flowchart
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

48. FP Arithmetic x /  Check for zero Add/subtract exponents
Multiply/divide significands (watch sign)
Normalize
Round
All intermediate results should be in double length storage
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

49. Floating Point Multiplication
1.xxxxx x 2bias+a x
1.yyyyy x 2bias+b
Floating Point Multiplication
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt

50. Floating Point Division
Sep 10, 2009
SYSC F09. SYSC2001-Ch9.ppt