1. Embedded
Embedded
at-speed test
at-speed test

2. Issues Multiple clock domains Multiple frequencies
Clock skew between clock domains
On-chip PLL generated clocks
Multiple PLLs for deskewing
Invalidation of delay tests
Overtesting (testing of sequential false paths)
Design of scan enable signals
Power dissipation
Ground bounce

3. Objectives Apply test with system timing in the capture window Clk1

4.          Multiple frequencies F1 F2 F3 Capture domain
Launch domain F2    F3

5. Multiple clock domains
Capture domain D1 D2 D3    D1   
Launch domain D2    D3

6. Single clock domain, single capture
last shift
capture
loading
unloading
Clk
shift mode
Sen
capture mode
Capture window: from last shift to capture
Scan enable has to propagate to all scan cells in less than one cycle
Overtesting - transitions may be launched from an illegal state
Delay test may be invalidated

7. Scan enable signal for at-speed scan
Scan enable signal designed as a clock tree
clock
scan enable

8. Pipelined scan enable signal
clock
scan enable

9. Speed of loading
Clock
suppression
Clock
suppression S C
Only the timing in capture window is crucial to at-speed testing
The loading and unloading frequency is irrelevant to at-speed testing
Slower frequency can be used to reduce power and constraints on test controller
Faster frequency can be used to reduce the test application time

10. Double capture Launch from a semi-legal state Reduced overtesting
Double time frame sequential fault simulation
Time
frame 1
Time
frame 2
first capture & transition launch
last shift
capture
Clk
Sen

11. “Slow” scan enable Scan enable signal has 1.5 cycle to propagate clock
last shift
capture
capture
first shift
Clock
suppression
Clock
suppression
Clk
Sen

12. Slow scan enable last shift launch capture first shift Sen Clk
Clock
suppression
Sen
Clk
Loading of random state

13. Slow scan enable last shift launch capture first shift Sen Clk
Clock
suppression
Sen
Clk
1. Initialization of internal nodes
2. Deactivation of scan enable
3. Propagation of scan enable signal (1.5 cycle)
4. Transition to a semi-legal state
5. Launch of transitions

14. Slow scan enable last shift launch capture first shift Sen Clk
Clock
suppression
Sen
Clk
1. Propagation of signals
2. Capture of responses

15. Slow scan enable last shift launch capture first shift Sen Clk
Clock
suppression
Sen
Clk
1. Activation of scan enable
2. Propagation of scan enable
3. First shift out of responses

16. Slow scan enable last shift launch capture first shift Sen Clk
Clock
suppression
Sen
Clk
Continued unloading of responses

17. Phase lock loop circuit
Frequency synthesis
Clock
fp = nfclk
PLL
fp / n

18. PLL deskewing
PLL1
Clock
PLL2
Deskewing No
Yes
global skew

19. Clock skew and race conditions
Clock skew results in race
Separate capture required

20. Fundamental principle
If clock skew is not managed between A and B
If there is logic driven by A and captured in B
There should be no simultaneous change of state in A and capture in B
Domain A
Domain B
Shift or capture
Capture

21. Multiple clock domains
Objective: at-speed testing of logic within every clock domain and between clock domains
BIST mode SE
CLK SE
CLK SE
CLK 
PLL
Test mode

22. Implementation - clock suppressed
suppression
Clock
suppression S C S* S* D1
Clock
suppression D2 S S C S* D3 S S S C
Robust operations assured with clock skew between domains
Captured and shifted data used as a stimuli for other domains
The order of capture can change in different vectors
Combinational fault simulation is sufficient as the response data is shifted out
One scan enable signal can be used for all domains

23. Implementation with hold states
Control SE H
scan
CLK S C S* H S* H D1 H C D2 S S S* D3 S S S C
Clock suppression replaced with hold state
Non-capturing domains put in hold state

24. Multiple frequencies - single capture
Load / unload window
Capture window
Clk1 C
Clk1*
Sen1 C
Clk2*
Sen2
All intra and inter domain logic is tested at speed
Combinational fault simulation is adequate

25. Slow enable and multiple frequencies
Clk1 C C
Clk1*
Sen1 C
Clk2*
Sen2

26. Multiple clock domains
Multiple clocks per capture cycle
All inter domain logic can be tested
Sequential fault simulation

27. Multiple clock domains – domain analysis
Merging non-interacting clock domains
Allows several clocks to be targeted at once
Reduces tester clock requirements
More efficient patterns
Better pattern count

28. clock signals feeding “BIST ready” netlist
Clock routing
clock signals feeding “BIST ready” netlist
Clock
Control
BIST
clock
Sin
Sen
Sout M I S R P R G
Scan
...
Sen
...
Scan
PLL
Shift counter
BIST Run
BIST
Done
hold
Pattern counter
External clock
source
BIST Reset

29. Embedded clock control
clk1 - fastest PLL output
Inputs from PLL
Capture waveform
generator for clk1
clk1 - out
Capture waveform
generator for clk2
clk2 - out
Capture waveform
generator for clk3
clk3 - out
BIST Run
Shift clock generator
(Clock divider)
Capture window
BIST clock

30. Summary Handling of multiple frequency and clock domains
Handling of very high speed designs with on-chip clocks
At-speed test in every inter- and intra-clock domain
Robust handling of clock skews through clock suppression and hold state
Separation of timing in loading-unloading and capture
No simultaneous change of state and capture in interacting domains without skew management
At-speed test is possible without at-speed scan
Power and ground bouncing can be managed by clock suppression and staggering in shift