1. 1 Finite State Machines (FSMs) Now that we understand sequential circuits, we can use them to build: Synchronous (Clocked) Finite State Machines Finite number of states Flip-flops/latches run on clock signal(s)

2. 2 FSM components: –Next state logic (combinational): next state = f(current state, inputs) –Memory (sequential): stores state in terms of state variables –Output logic (combinational): function depends on FSM type: Moore Machine: output = g(current state) Mealy Machine: output= g(current state, inputs)

3. 3 FSM Analysis Goal: Given a FSM circuit, describe the circuit’s behavior

4. 4 Excitation equations describe memory (FF or latch) input signals as a function of inputs and current state (i.e., state variables) Excitation Equations:

5. 5 Transition equations describe the next state as a function of inputs and current state –Generated by substituting the excitation equations into the characteristic equation for the sequential gates Transition Equations:D FF Characteristic Eqn: This step is trivial when using D FFs!

6. 6 Output equations describe the output signals as a function of the current state (for a Moore machine) or as a function of the current state and inputs (for a Mealy machine) Output Equation:

7. 7 The transition/output table shows the next state and output for every current state/input combination –Entries of the table are obtained from the transition equations and the output equations Transition Equations: Output Equation: Transition/Output Table:

8. 8 State labels are a one-to-one mapping from state encodings to state names The state/output table has the same format as the transition table, but state names are substituted in for state encodings Transition/Output Table:State/Output Table:

9. 9 A state diagram is a graphical representation of the information in the state/output table Nodes (or vertices) represent states –Moore machines: output values are written in state node Arcs (or edges) represent state transitions –Labeled with a transition expression when an arc’s transition expression evaluates to 1 for a given input combination, that arc is followed to the next state –Mealy machines: output values (or expressions) are written on arcs State/Output Table: State Diagram:

10. 10 FSM Analysis Recap 1)Find the circuit’s excitation equations 2)Using the excitation and characteristic equations, write the circuit’s transition equations 3)Write the circuit’s output equations 4)From the transition and output equations, create the circuit’s transition/output table 5)Create state labels 6)Using the transition table and state labels, create the state table 7)(optional) Draw the circuit’s state diagram

11. 11 FSM Design Goal: Design a FSM that satisfies the requirements of the given problem description (spec.) Follow FSM analysis steps in reverse! (more or less) 1)(optional) Construct state diagram 2)Construct state/output table 3)Create state assignments 4)Create transition/output table 5)Choose FF type 6)Construct excitation/output table - Similar to transition/output table 7)Find excitation and output logic equations “Art of design” “Turn the crank”

12. 12 FSM Design Example Problem description: design a Moore FSM with one input IN and one output OUT, such that OUT is one iff IN is 1 for three consecutive clock cycles State table:

13. 13 State Assignments –How many state variables are needed to encode four states? –In general, if we have n states, how many state variables are needed to encode those states? These state assignments may seem rather arbitrary – that’s because they are! We will soon see the impact that state assignments have on our final circuit…

14. 14 Transition/output table Choose FF type: –Using D flip-flops will simplify things (as we’ll see below…) Excitation table –Shows FF input values required to create next state values for every current state/input combination –If we’re designing with D FFs, entries in excitation/output table are the same as those in transition/output table! Because of D FF characteristic equation: Q + = D State/Output Table:Transition/Output Table:

15. 15 Excitation Logic Output Logic Excitation/Output Table:

16. 16 Circuit: Excitation Equations:Output Equation:

17. 17 In Class Exercise Design a state/output table for the following problem specification: Combination lock: Two inputs, X and Y, encode a binary number between 0 and 3 (X is MSB, i.e., XY = 10 →2). A single output signal UNLOCK should be set to 1 iff the sequence 1, 2, 1 occurs on the inputs in three consecutive clock cycles

18. 18 FSM Transition List Design: 50’s Vending Machine Inputs –d: asserted when user inserts dime –n: asserted when user inserts nickel –c: asserted when user presses candy button –s: asserted when user presses soda button Outputs –dc: dispenses candy when asserted –ds: dispenses soda when asserted –cr: 4-bit unsigned number, represents the user’s credit Specifications –All inputs are one-hot –Candy costs 10 cents, soda costs 15 cents –Money need only be counted up to 15 cents

19. 19 Vending Machine State Diagram and Transition List

20. 20 …

21. 21 50’s Vending Machine: Mealy Implementation The Mealy implementation uses fewer states, and therefore fewer FFs!

22. 22 State Assignments Back to our combinational lock example… Minimal SOP: 26 literals Perhaps we can do better using smarter state assignments… Minimal POS: 20 literals

23. 23 Another state assignment approach –Maximize the number of 1’s Using smarter state assignments improved the next-state circuit cost from 20 literals to 9 literals! Minimal SOP: 10 literals Minimal POS: 9 literals

24. 24 Another approach: use more flip-flops –one-hot encodings (with the addition of 000) Read minterms directly off of transition table: 23 literals How many states are really in our new state machine? What happened to the other 4 states???

25. 25 Unused States Previous design: all unused states were implicitly assigned a next state of 000 (state A) This is known as a safe design –If noise causes the machine to enter an unused state, it will return to a used state under any input conditions

26. 26 Efficient Design: Treat the next-states and outputs of unused states as don’t cares –Minimizes circuit cost! If an unused state is ever entered, state machine may never return to normal operation Finding transition equations now requires 5-variable K-maps!

27. 27 State clustering assigns unused states to behave like used states If noise causes an unused state to be entered, the machine will return to a used state in a single clock cycle