1. AT91 Memory Interface

2. 2 Features –Up to 8 programmable chip select lines –Remap Command allows dynamic exception vectors –Glue-less for both 8-bit and 16-bit standard memories –16-bit memories emulated with 2 8-bit memories –Up to 8 Wait States can be programmed –External wait request supported –Early Read protocol allows faster clock with slower RAM –Data Float Time programming (up to 7) allows connections of high tDF devices External Bus Interface (1/2)

3. 3 Block Diagram External Bus Interface (2/2)

4. 4 Select the most cost effective 16-bit memory implementation –Byte Select Access Type : one actual 16-bit memory –Byte Write Access Type : 2 8-bit memories Byte Access Type

5. 5 Standard RAM connections

6. 6 Standard Flash connections

7. 7 The Early Read Protocol

8. 8 In Early Read Protocol, the EBI adds automatically one wait state after an external write access to remove any Data Bus contention risks Early Read Wait State

9. 9 Standard Programmable Wait States Read Cycle Waveform Write Cycle Waveform

10. 10 Parameters to be considered –t CE = 90ns max –t OE = 40ns max So, the requirements are (std read) –nt CP - EBI 4 - EBI 25  t CE –nt CP - t CP /2 - EBI 22 - EBI 25  t OE Calculating required standard wait states with AC Characteristics (1/2) AT91M55800A EBI Timings @ 32MHz AT49BV1604-90 Read Timings

11. 11 Parameters to be considered: –t WP = 100ns min –t DS = 100ns min So, the requirements are: –(n-1)t CP - EBI 8 + EBI 10  t WP –(n-1)t CP - EBI 11 + EBI 10  t DS Calculating required standard wait states with AC Characteristics (2/2) AT91M55800A EBI Timings @ 32MHz AT49BV1604 -90 Write Timings

12. 12 External Wait States To access slow peripherals with more than 8 Wait States NWAIT assertion stops the internal Wait States counter Setup and Hold times to respect, regarding the MCK rising edge So it may be necessary to program one standard Wait State to take into account the decode logic latency

13. 13 Data Float helps to support devices very slow in releasing the Data Bus –Read Device a 2 tdf cycle –Read Device b 3 tdf cycle Data Float Time Data Float Time cycles includes internal access cycle Read Device a 2 tdf cycle Internal Access Read Device b 3 tdf cycle

14. 14 Default Memory 0 configuration : –CSR0 = 0x0000203D or 0x0000203E 8 wait states 0 data float time 8/16 bits data bus width selected by BMS if 16 bits data bus width is selected, byte access type is not significant, because continuous read is made in memory 0 Speed up of the boot sequence before remap –can be performed by writing EBI_CSR0 Base addresses are defined in EBI registers In EBI_CSR0 for Memory 0 generally corresponds to the link address Boot Mode and Remap Command

15. 15 Allows to reach the maximum of performance in Thumb Mode –That’s ARM highest performance allowed with a 16-bit bus ! Emulates 2 8-bit memories as a 16-bit one Supports any kind of 8-bit or 16-bit static memory –Select the most cost effective memory solution Remap Command maps exception vectors in internal SRAM –Fast Interrupt Handling –Dynamic Exception Vectors External Bus Interface Benefits