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VHDL Basics. VHDL BASICS 2 OUTLINE –Component model –Code model –Entity –Architecture –Identifiers and objects –Operations for relations VHDL ET062G &

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Presentation on theme: "VHDL Basics. VHDL BASICS 2 OUTLINE –Component model –Code model –Entity –Architecture –Identifiers and objects –Operations for relations VHDL ET062G &"— Presentation transcript:

1 VHDL Basics

2 VHDL BASICS 2 OUTLINE –Component model –Code model –Entity –Architecture –Identifiers and objects –Operations for relations VHDL ET062G & ET063GNajeem Lawal, 2012

3 COMPONENT MODEL 3 MODEL FOR DESCRIBING COMPONENTS –External interface –Internal function A B C X Y Ports: external connections to the component The component’s - Behaviour or - Structure VHDL-component Function: a number of parallel processes VHDL ET062G & ET063GNajeem Lawal, 2012

4 DESCRIPTION MODEL VHDL-component Function - architecture Interface - Entity with ports Declaration of entity Declaration of architecture VHDL ET062G & ET063G4Najeem Lawal, 2012

5 DECLARE THE INTERFACE OF THE VHDL- COMPONENT 5 entity mux2 is port ( a: in STD_LOGIC; b: in STD_LOGIC; sel: in STD_LOGIC; y: out STD_LOGIC; ); end mux2; MUX 2-1 y sel a b VHDL ET062G & ET063GNajeem Lawal, 2012

6 THE PORTS OF THE VHDL-COMPONENT 6 entity mux2 is port ( a: in STD_LOGIC; b: in STD_LOGIC; sel: in STD_LOGIC; y: out STD_LOGIC; ); end mux2; port defines inputs and outputs in/out defines the mode of the port Determines the direction of the dataflow std_logic is the datatype for the inputs and output VHDL ET062G & ET063GNajeem Lawal, 2012

7 PORTS IN VHDL 7 PORT-DECLARATION IS THE MOST IMPORTANT THING IN THE ENTITY-DECLARATION EACH PORT REPRESENTS –The external pins of the component EACH PORT HAS A –Port-name –Mode –Datatype An identifier that you create Direction of dataWhich values to port can be assigned VHDL ET062G & ET063GNajeem Lawal, 2012

8 THE MODES OF THE PORT 8 INOUT BUFFER INOUT The signal goes only in to the component and the value is driven by another component. The input signal is used on the right side in the assignment: z <= a OR inport The signal goes out from the component. It is not possible to read the value of the output. Is used on the left side in the assignment: outport <= a OR b The signal goes out from the component. It is possible to read back the value of the output. Can be used on both sides in the assignment: buffer_port <= a OR b; z <= buffer_port OR c; The signal can go in both directions, either in or out -The value of the signal can be read by the component -The signal can be driven by other components -Can be used in both sides in an assignment VHDL ET062G & ET063GNajeem Lawal, 2012

9 DESCRIBING THE FUNCTION IN THE ARCHITECTURE 9 In the architecture the function is described: If sel is 0 then the value of a is put on the output y. Otherwise (sel=1) the value of b is put on the output y. architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; MUX 2-1 y sel a b VHDL ET062G & ET063GNajeem Lawal, 2012

10 DECLARATION OF THE ARCHITECTURE 10 begin … end for the architecture begin … end for the process Sequential statements (if-then-else) in the process Process with sensitivity-list Name of the entity Name of the architecture architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; VHDL ET062G & ET063GNajeem Lawal, 2012

11 STRUCTURE OF THE ARCHITECTURE 11 architecture name_arch of name is begin end name_arch; Declaration of signals Parallella satser Process 1 Parallel statements Process 2 Parallel statements Processes and parallell statements are executed in parallel Inside a process the execution is sequential Signals are used for communication between components and parallel statements. Signals can only be declared at architecture-level (not in processes) VHDL ET062G & ET063GNajeem Lawal, 2012

12 EXAMPLE OF PARALLEL AND SEQUENTIAL STATEMENTS 12 Parallel processes ENTITY ename IS Ports( a, b, c: IN bit; y, z, w: OUT bit; Declarations -- no variables allowed END ename ARCHITECTURE first OF ename IS Declarations -- no variables, but signals are OK BEGIN y <= a AND b; PROCESS (a,b,c) Declarations -- no signals, but variables are OK VARIABLE v: bit; BEGIN v := (a OR b); v := v AND c; w <= a XOR v; END PROCESS; z <= c XOR b; END first; Statements in proce- sses are sequential VHDL ET062G & ET063GNajeem Lawal, 2012

13 IDENTIFIERS IN VHDL 13 IDENTIFIERS –Are names of things that you create –E.g. names for architectures, entities, processes, variables, signals –Rules for naming Cannot be a reserved word in VHDL (e.g. for, if) VHDL is case-insensitive First character must be a letter Last character cannot be underscore (_) Two consecutive underscores are not allowed VHDL ET062G & ET063GNajeem Lawal, 2012

14 OBJECTS IN VHDL 14 OBJECTS CAN HOLD A VALUE –Objects have class and type Class determines what kind of operations can be performed on the object Type determines what values the object can hold –Objects can be initialized (only for simulation) –They are declared in entity, architecture, process, or package VHDL ET062G & ET063GNajeem Lawal, 2012

15 CLASSES IN VHDL 15 SIGNAL –Their values are changed as a function of time –They have a signal-driver and can be seen upon as a wire VARIABLE –Their values are changed immediately after assignment –No timing is related to variables CONSTANT –Their values cannot be changed FILE –Values to and from external file can be accessed VHDL ET062G & ET063GNajeem Lawal, 2012

16 DATA TYPES IN VHDL 16 VHDL HAS HARD REQUIREMENTS ON TYPING –Objects of different types cannot be mixed –Functions for type-conversion must be used TWO MAIN CATEGORIES OF DATATYPES –Scalar Can be assigned one single value Examples: enumeration, integer, float, physical –Composite Can be assigned multiple values Examples: array, record VHDL ET062G & ET063GNajeem Lawal, 2012

17 SCALAR 17 ENUMERATION –A list of discrete values the variable can be assigned to –Ex: type weekday = (mon, tue, wed, thu, fri, sat, sun); INTEGER –A set integers – positive or negative –A pre-defined datatype –Integer is of 32-bits with sign –2 31 to +(2 31 -1) –When describing hardware a limited range can be used Ex: variable num: integer range –64 to 64 VHDL ET062G & ET063GNajeem Lawal, 2012

18 SCALAR 18 FLOATING-POINT –Pre-defined datatype is real –32-bits single precision –Is never used for describing hardware Will result in too complex hardware PHYSICAL –Datatype for physical units Ex. time, mA, Volt Has no meaning for describing hardware VHDL ET062G & ET063GNajeem Lawal, 2012

19 EXAMPLES OF ENUMERATED DATATYPES 19 PRE-DEFINED TYPES (1076) – type boolean is (FALSE, TRUE); – type bit is (’0’,’1’); PRE-DEFINED TYPES (1164) –Std_logic –Std_ulogic –Arrays of these types and sub-types –Access to these types by including: LIBRARY ieee; USE ieee.std_logic_1164.all; VHDL ET062G & ET063GNajeem Lawal, 2012

20 STD_LOGIC 20 First in the VHDL to include libraries (packages) library IEEE; use IEEE.std_logic_1164.all; type std_ulogic is (‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’);-- Don’t care subtype std_logic is resolved std_ulogic; Definition av std_logic VHDL ET062G & ET063GNajeem Lawal, 2012

21 COMPOSITE DATA TYPES 21 ARRAYS –Examples of declarations of 8-bit vectors signal s1: bit_vector(7 downto 0); variable v1: bit_vector(7 downto 0); –Assignment of the bit vector 11010010 s1 <= ”11010010”; v1 := ”11010010”; Most significant bit Least significant bit VHDL ET062G & ET063GNajeem Lawal, 2012

22 COMPOSITE DATA TYPES 22 EX: TWO-DIMENSIONAL ARRAY – type table6x2 is array (0 to 5, 1 downto 0) of bit; – constant mytable: table6x2 := (”00”,”01”,”10”,”11”,”01”,”01”); EX: BIT VECTORS FOR BINARY, OCTAL AND HEXADECIMAL NUMBERS X”A3”-- = B”1010_0011” for a 8-bits vector O”27”-- = B”010_111” for a 6-bits vector ’0’’1’ ’0’ ’1’ 1 0 12340 ’0’ ’1’ 5 VHDL ET062G & ET063GNajeem Lawal, 2012

23 ATTRIBUTE 23 ATTRIBUTE –Holds information about a signal, variable, data type, function. –Example #1 type bitcount is integer range –3 to +5; -3-20+1+2+3+4+5 bitcount’leftbitcount’right bitcount’lowbitcount’high VHDL ET062G & ET063GNajeem Lawal, 2012

24 ATTRIBUTE 24 –Example #2 type byte is array (7 downto 0) of std_logic; 65437210 byte’leftbyte’right byte’lowbyte’high Example #3 for i in byte’high downto byte’low loop v_byte(i) := ’1’; end loop; i goes from 7 down to 0 VHDL ET062G & ET063GNajeem Lawal, 2012

25 OPERATORS IN VHDL 25 OPERATORS FOR RELATIONS ARITHMETIC OPERATIONER Supported by synthesis tools SymbolOperation =equal /=Un-equal <Less than >Greater than <=Less-equal >=Greater-equal SymbolOperation +addidion -subtraktion *multiplikation /division absAbsolute value remremainder modmodulus **exponent VHDL ET062G & ET063GNajeem Lawal, 2012

26 ESSENTIALS IN VHDL 26 JKHHJ entity entity_name is end entity entity_name; port ( port_name : MODE(e.g. IN) DATA_TYPE(e.g. STD_LOGIC) ); architecture arch_name of entity_name is SIGNAL sig_name : data_type := initial_value; begin parallel statements; end architecture arch_name; pro_label: process( sensitivity list) variable var_name : data_type := initial_value; Begin sequential statements; end process pro_label; Library ieee; Use ieee.PACKAGE_NAME.function VHDL ET062G & ET063GNajeem Lawal, 2012

27 ESSENTIALS IN VHDL 27 Library ieee; Use ieee.std_logic_1164.ALL; entity mux2 is port ( a: in STD_LOGIC; b: in STD_LOGIC; sel: in STD_LOGIC; y: out STD_LOGIC; ); end mux2; architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; VHDL ET062G & ET063GNajeem Lawal, 2012

28 ESSENTIALS IN VHDL 28 architecture struct_arch of entity_name COMPONENT component_name PORT( port_name : MODE data_type; ); END COMPONENT; SIGNAL connecting signale : data_type := initial_value; Begin instance_name : component_name PORT MAP ( port_name => connecting_signal, ); End architecture struct_arch; VHDL ET062G & ET063GNajeem Lawal, 2012

29 END OF LECTURE 2 29 Outline Component model Code model Entity Architecture Identifiers and objects Operations for relations VHDL ET062G & ET063GNajeem Lawal, 2012

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