1. A serial powering scheme for the ATLAS pixel detector at sLHC L. Gonella, D. Arutinov, A. Eyring, M. Barbero, F. Hügging, M. Karagounis, H. Krüger, N. Wermes TWEPP 2010, Aachen, 21/09/2010

2. Outlook  ATLAS pixels powering needs  Serial powering  Serial powering scheme for ATLAS pixels @ sLHC  Scheme architecture  Shunt-LDO  AC-coupling  Stave protection  Prototyping status  Material budget calculations  Conclusions 2L. Gonella - TWEPP 2010 - 21/09/2010

3. ATLAS pixels powering LHC  sLHC FE channels:~80M  ~455M Total FE power:6.7kW  12.3kW Total FE current:3.8kA  6kA  @LHC: independent powering  20% efficiency  Very massive services  High x/X0%, saturated cable channels  @sLHC  Independent powering is unfeasible!  Need to transmit power at low currents  lower V drop  Higher power efficiency  Reduced cables cross section  Serial powering or DC-DC conversion x5-6 granularity x2 power x3 current  ATLAS inner det. material distribution (incl. IBL) 3L. Gonella - TWEPP 2010 - 21/09/2010

4. Serial powering  Allows transmitting power at low currents and high voltages  A chain of n modules is powered in series by a constant current I  Current to voltage conversion is performed locally (on chip/module) by regulators  Key facts  I scales of a factor n, with respect to parallel powering  V drop is limited only by the power density and the I source output voltage capability  Allows optimal trade off between efficiency and material parallel powering serial powering 4L. Gonella - TWEPP 2010 - 21/09/2010

5. Regulators: on or off chip? Ratio of converter/detector Figure Of Merits (FOM)  radiation thickness penalty for using converters in active areas  FOM for silicon detectors: (load resistance) x (active area)  Pixels = 10 Ω ·cm 2  Strips = 100 Ω ·cm 2  FOM for converters: ε /(1- ε ) x (output resistance) x (x/X0) x (area)  External converters =1-5% x/X0· Ω ·cm 2 @ 80% efficiency  Penalty for pixels = 0.5% x/X0 per layer  Penalty for strips = 0.05% x/X0 per layer  Strips can use external converters  Pixels must use internal/on chip converters  Penalty >0.2% x/X0 per layer too severe  Target for ATLAS pixels @ sLHC < 2% x/X0 per layer 5L. Gonella - TWEPP 2010 - 21/09/2010

6. On-chip regulators for SP  FE needs analog and digital voltage  2 regulators/FE  Redundancy  Connect all regulators on module that take I in in parallel  In case of failure of one regulator, the current can still flow through the other regulators on the module and the power chain is not interrupted REGULATOR REQUIREMENTS Very robust against mismatch and process variation Able to cope with increased input current  6L. Gonella - TWEPP 2010 - 21/09/2010

7. System aspects AC-coupled module readout Stave protection  Modules in a chain are on different gnd  Assure supply of power to the SP chain in case of failures  Allow power to arbitrary selection of modules  Requirements  Slow Control  Fast Response  Low power density  Minimal x/X0  Radiation hardness Protection Module AC-coupled readout 7L. Gonella - TWEPP 2010 - 21/09/2010

8. SP for ATLAS pixels @sLHC  Starting point for development of a SP scheme: pixel outer layers  Technology to build them is available  Planar sensors on 6” wafer  FE-I4 with minor differences wrt. IBL  GBT system for data  A stave concept is being developed  Entering the prototyping phase Current pixel detector layout 4 barrel layers (5 th one considered) 5 disks/side 8L. Gonella - TWEPP 2010 - 21/09/2010

9. sLHC outer layers  32 modules/stave  16 top, 16 bottom  2x2 FE-I4 modules  Electrical unit = ¼ stave (i.e. 8 modules)  1 stave cable/el. unit  1 EOS card/el. unit 42.6 38.0 35.9 Active 33.9 x 40.6 10.0 15.0 Flex pigtail (connector plugs into page) ‏ Pixel orientation Flex down to chip w-bonds Module top view glue FE sensor flex connector Compressed scale 1.0 mm stiffener passives FE Module side view 9L. Gonella - TWEPP 2010 - 21/09/2010

10. Current (i.e. power) to the modules  Current delivered to the modules via stave cable and module flex  Power unit = electrical unit = 8 modules  I tot = I mod = ~2.4 A  FE-I4 nominal current = ~600 mA  Current to voltage conversion on-chip  Shunt-LDO  2 Shunt-LDO/FE to generate VDDA = 1.5 V and VDDD = 1.2 V  8 Shunt-LDO on the module operate in parallel IinIout Shunt-LDO 1.5V1.2V FE-I4 Shunt-LDO 1.5V1.2V FE-I4 Shunt-LDO 1.5V1.2V FE-I4 Shunt-LDO 1.5V1.2V FE-I4 I in I out 10L. Gonella - TWEPP 2010 - 21/09/2010

11. Shunt-LDO working principle Combination of an LDO and a shunt transistor Shunt regulation circuitry  const I load LDO regulation loop  constant V out Shunt-LDO: simplified schematic LDO compensates V out difference 2 Shunt-LDOs in parallel: equivalent circuit  Shunt-LDO can be placed in parallel without problems due to mismatch  Shunt-LDO with different V out can be placed in parallel  Shunt-LDO can cope with increased I in  Normal LDO operation when shunt circuitry is off 11L. Gonella - TWEPP 2010 - 21/09/2010

12. Shunt-LDO characterization Working principle and good performance demonstrated by 2 prototypes 2 Shunt-LDO in parallel generating different V out Load regulation  V in and V out stable until (I load1 + I load2 ) = I supply (= 0.8 A)  Effective R out = 60 m Ω (incl. wire bonds and PCB traces) V out generation  After saturation  V out settle @ different potentials  R in ≈ 2 Ω 12L. Gonella - TWEPP 2010 - 21/09/2010

13. Shunt-LDO in a serial powering chain Shunt-LDO 0Shunt-LDO 2 Shunt-LDO 1Shunt-LDO 3 4 Shunt-LDOs in series generating V out = 1.5V 13L. Gonella - TWEPP 2010 - 21/09/2010 Shunt-LDO 0 Shunt-LDO 1 Shunt-LDO 2 Shunt-LDO 3 I source

14. Shunt-LDO efficiency  Shunt-LDO sources of inefficiency  LDO dropout voltage V drop  I shunt  Δ V between the 2 V out needed by the FE  Calculation for ATLAS Pixels nominalworst casebest V out1 [V]1.4 V out2 [V]1.2 I out1 [A]0.360.40.36 I out2 [A]0.240.270.24 V drop [V]0.2 0.1 I shunt [A]0.030.050.01 Δ U [V]0.20.30.2 I TOT [A]0.60.670.6 P_eff, 180.77%77.78%90.81% P_eff, 266.67%59.56%76.80% P_eff, 1-279.55%76.14%90.32% ΔP_eff,1-24.55%6.57%5.16% P_eff,1-2g75.00%69.56%85.16% 14L. Gonella - TWEPP 2010 - 21/09/2010

15. AC-coupling Widely used termination technique in telecommunications  Optimal V CM at RX input  Level shifting  Guard against differences in ground potential  Needed for module readout in a serial powering scheme  Independently of the powering scheme might be needed for the ATLAS pixels upgrade  @IBL  Concerns about long data transmission lines  Discussion already started about possible need for AC- coupling  @sLHC  Possible compatibility issues between FE-I4 and GBT standards  LVDS vs. JESD8-13: SLVS-400 6-7m 15L. Gonella - TWEPP 2010 - 21/09/2010

16. Possible AC-coupling implementations Favorite option: direct AC-coupling at RX input Simple, low material Requires self biased RX input & DC-balanced data Downlink: clk & cmd  FE-I4 RX input self biased  clk inherently DC-balanced  cmd are not DC balanced but  Slow data (40MHz)  Rail-to-rail receiver, i.e. can accommodate some V CM shift arising from non-DC balanced data Uplink: data  FE-I4 data are 8b10b encoded  GBT accepts any encoding  RX inputs do not have integrated self biasing circuitry, but this could eventually be done externally Alternative option: link with feedback Successfully used for the SP proof of principle Higher complexity, more material 16L. Gonella - TWEPP 2010 - 21/09/2010

17. Stave protection Proposed protection scheme  1 Module Protection Chip/module  Could be placed on pigtail  1 AC-coupled slow ctrl line/MPC from the DCS  8 lines/stave cables  One capacitor/line on the DCS side MPC flex sensor FE connector stiffener module MPC module DCS MPC Working principle  DCS can switch on/off selected modules via slow ctrl line  In case of overvoltage  Fast response circuitry in MPC reacts  DCS switches off the module  MPC can be used also for power on sequence 17L. Gonella - TWEPP 2010 - 21/09/2010

18. Module protection chip C1 M bp local VDD DCS GND ADC C2 D1 D2 local GND OV D3 module Iin Iout  130nm IBM  Bypass transistor  Independent slow ctrl line & OV protection  OV protection = Silicon controlled rectifier  Preliminary simulations: V gs bp AC-signal V mod I mod I bp Slow ctrl I bp V mod V gs bp ~850mV Fast response C1 = 100nf C2 = Cgs = 33pf D1, D2 = PMOS Bypass DGNMOS W = 48mm L = 0.24µm 18L. Gonella - TWEPP 2010 - 21/09/2010 V (V) I (A) time (ms) r ( Ω ) time (ms)

19. Prototyping Goal: prototyping an sLHC pixels outer layer with serial powering to try the concept extensively  Outer pixel layers prototyping started in the pixel collaboration  4-chip sensor design in production, FE-I4 submitted  stave cable and type1 cables already prototyped  In progress: stave mechanics and cooling studies, EOS cards design, …  Serial powering related activities in Bonn  Design of LV lines on stave cables  Design of module flex: 1 st prototype in production  Allows testing SP, direct powering, direct powering with DC-DC Stave cable Module flex 19L. Gonella - TWEPP 2010 - 21/09/2010

20. x/X0: SP vs. DC-DC – active area x/X0% SP x/X0% DC-DC (%) Direct powering with DC-DC conv  fixed V drop between V source and converter @sLHC: voltage regulator on PP1, x2 charge pump DC-DC converter in FE-I4  0.2V on stave, 0.8V on Type 1 services DC-DC conv: Vdrop = 0.2V  P cable = 5.56% P tot  LV cables: 0.093% x/X0 SP @ P cable = 5.88% P tot  LV cables = 0.014% x/X0  ~85% less material Serial powering LV lines (Al + kapton):0.056% x/X0 AC-coupling C:0.018% x/X0 Protection: 0.010% x/X0 Total:0.084% x/X0 Direct powering w/ DC-DC conversion LV cable (Al + kapton):0.139% x/X0 External C: 0.015% x/X0 Total:0.154% x/X0 x/X0% LV lines (Al only) 20L. Gonella - TWEPP 2010 - 21/09/2010

21. x/X0: SP vs. DC-DC – large η  Services dominate the material budget  Cable channels are saturated ATLAS inner det. material distribution (incl. IBL) DC-DC conv: V drop = 0.8V  LV cables: 2827.2mm 2 Al x-section SP @ V drop = 0.8V  LV cables: 684mm 2 Al x-section x/X0 SP ≤ 0.25 x/X0 DC-DC 21L. Gonella - TWEPP 2010 - 21/09/2010

22. Conclusions  Scheme architecture definition, power efficiency and material budget calculations ongoing  A custom developed new regulator concept targeting serial powering has been developed: Shunt-LDO  2 prototypes confirmed working principle and good performance  2 Shunt-LDOs/FE-I4  AC-coupling and protection schemes have been proposed  FE-I4 LVDS RX designed with self-biased inputs for direct AC-coupling with DC-balanced data  Simulation of a Module Protection Chip started  Prototyping of an ATLAS pixel detector outer layer featuring serial powering for sLHC has started A serial powering scheme for the ATLAS pixel detector at sLHC is being developed at Bonn University 22L. Gonella - TWEPP 2010 - 21/09/2010

23. On-chip voltage generation: basic  2 regulators/FE to generate analog and digital V  For redundancy, connect all regulators on a module that take I in in parallel  Example  1 shunt + 1 LDO / FE  The shunt regulator takes I in and generates V dd  The LDO takes V dd as input and generates V dda  Connect all shunt regulators on a module in parallel  Enhance the stability of the output voltage → the internal resistances are also in parallel → lower total resistance → steeper I-V characteristic  Steep I-V characteristic + Different V out due to mismatch & process variation → At turn on most of the shunt current will flow to the regulator with lowest V out → Potential risk of device break down at turn on → Use an input series resistor to reduce the slope of the I- V characteristic and help distributing the shunt current between the parallel placed regulators  R does not contribute to the regulation and consumes additional power  Requirements for the regulator  Very robust against mismatch and process variation  Able to cope with increased input current I in V dd V dda LDO Shunt without resistor Iin[mA] with resistor Vout[V] 750 500 250 0 0 0.5 1 1.5 2 23L. Gonella - TWEPP 2010 - 21/09/2010

24. Shunt-LDO: working principle  Combination of a LDO and a shunt transistor  R slope of the shunt is replaced by the LDO power transistor  Shunt transistor is part of the LDO load  Shunt regulation circuitry ensures constant I load  I ref set by R3, depends on V in (  I in )  I M1 mirrored and drained in M5  I M1 and I ref compared in A3  M4 shunts the current not drawn by the load  LDO regulation loop sets constant output voltage V out  LDO compensates output potential difference simplified schematics 24L. Gonella - TWEPP 2010 - 21/09/2010

25. Shunt-LDO: features  Also, Shunt-LDO regulators having different output voltages can be placed in parallel  Extra V at the input of the regulator with lower output voltage drops across its LDO  Shunt-LDO can cope with an increased supply current if one FE-I4 does not contribute to the regulation e.g. disconnected wire bond  I shunt will increase  Shunt-LDO can be used as an ordinary LDO when shunt is disabled Parallel placed regulators with different output voltages - simulation results - slope = R3/mirror ratio Current splits equally between the 2 regulators V out = 1.5V V out = 1.2V  Shunt-LDO regulators can be placed in parallel without any problem regarding mismatch & shunt current distribution  Resistor R3 mismatch will lead to some variation of shunt current (10-20%) but will not destroy the regulator 25L. Gonella - TWEPP 2010 - 21/09/2010

26. Shunt-LDO: prototypes and test system  Test setup  Two Shunt-LDO regulators connected in parallel on the PCB  Biasing & reference voltage is provided externally  Input & load current is provided by programmable Keithley sourcemeter  Input & output voltages are measured automatically using a Labview based system  Shunt current is measured by 10m Ω series resistors and instrumentation opamp  2 prototypes submitted and tested  September 2008, March 2009  V out = 1.2-1.5 V, V dropout MIN = 200 mV, I shunt MAX = 0.5 A, R in = 4 Ω, R out = 30 m Ω 26L. Gonella - TWEPP 2010 - 21/09/2010

27. 2 Shunt-LDO in parallel  Load regulation measurement  1.5(1.2) V output sees fix I load = 0.4 A  1.2(1.5) V output has variable I load  V in and V out collapse when the overall I load reaches I supply (= 0.8 A)  Effective output impedance R = 60 m Ω (incl. wire bonds and PCB traces)  Generation of different V out  V out settles at different potentials  V out1 and V out2 slightly decrease with rising input current (V drop on ground rails leads to smaller effective reference voltages)  Non constant slope of V in  R in ≈ 2 Ω (after saturation) 27L. Gonella - TWEPP 2010 - 21/09/2010

28. Shunt current distribution at start-up  Unbalanced I shunt distribution at start-up  More I shunt flows to the regulator which saturates first (i.e. to the regulator with lower V out )  However I shunt MAX is not exceed  Improvement of shunt distribution as soon as both transistors are saturated  Non - constant slope of V in closely related to I shunt distribution 1 st prototype 2 nd prototype 2 SHULDOs in parallel with different V out  Bad mirroring accuracy for non saturated transistors due to offset at the input of A2  Wrong current is compared to the reference  Hypothesis confirmed by simulations and second prototype  Scaling of input transistor of A2 by factor 4 halves the unbalance 28L. Gonella - TWEPP 2010 - 21/09/2010

29. Shunt current distribution  No problem at start-up if the 2 SHULDOs generate the same V out  They saturate at the same time  If V out is changed with both regulators being saturated the shunt current changes of about 1.4%  Unbalanced I shunt at start-up can be avoided completely by choosing the same V out at start-up and setting different V out afterwards Vout1 fixed at 1.2 V Vout2 varies ( 1.2 – 1.5 V ) 2 SHULDOs in parallel with same V out at start-up 29L. Gonella - TWEPP 2010 - 21/09/2010

30. SHULDO: Load Transient Behavior  I load pulse of 150mA (15mV measured across 100m Ω )  10mV output voltage change load pulse V out 30L. Gonella - TWEPP 2010 - 21/09/2010

31. SHULDO Efficiency 31L. Gonella - TWEPP 2010 - 21/09/2010

32. SHULDO Efficiency 32L. Gonella - TWEPP 2010 - 21/09/2010

33. Self-biased RX input: Simulation Results 33L. Gonella - TWEPP 2010 - 21/09/2010

34. Self-biased RX input: Start-Up 34L. Gonella - TWEPP 2010 - 21/09/2010

35. Self-biased RX input: Almost Steady State 35L. Gonella - TWEPP 2010 - 21/09/2010

36. Module Protection Chip  130nm CMOS technology  Bypass transistor  AC-coupled slow control line  can be used to monitor V mod when idle  Independent over voltage protection circuitry  Specs for 4-chip FE-I4 module (*)  I nom = 2.4A, I MAX = 3.5A  AC-signal frequency = 100k – 1MHz  AC-signal amplitude = V gs bypass  OV protection threshold: V thMIN = 2V – V thMAX = 2.5V  OV protection time response = 100ns C1 M bp local VDD DCS GND ADC C2 D1 D2 local GND OV D3 module Iin Iout (*) preliminary 36L. Gonella - TWEPP 2010 - 21/09/2010

37. Bypass Transistor  I = 3.5A, V ≥ 1.6V (max 2.5V)  DG NMOS  Radiation hardness  ELT to cut leakage current path  Positive V th shift at TID ≥ 1Mrad  Account for Δ V th = 200mV in simulations  Operational temperature  Not yet defined, will depend on the sensor  Simulations with T = (-27 ÷ +27) o C  Low power consumption when on  Process Corners  W = 48mm, L = 0.24µm M bp local GND local VDD Shunt-LDO I in I out 1.4/1.2V V drop (min) = 200mV  Power consumption (worst case)  Bypass on  335.1mW  Bypass off  25µW 37L. Gonella - TWEPP 2010 - 21/09/2010

38. Control Line  Rectifier  In a diode connected MOSFET V ds = V gs ≈ V th  To increase the power conversion efficiency  V sb < 0 when diode is forward biased  V th smaller  V ds smaller  V sb > 0 when diode is reversed biased  V th higher  smaller leakage current  use PMOS or triple well NMOS (allow to connect bulk in the “forward direction”)  Thin oxide transistor  W = 10µm for radiation hardness  2 PMOS in series to avoid gate oxide breakdown (AC-signal amplitude > 2.5V) 38L. Gonella - TWEPP 2010 - 21/09/2010

39. Control Line: Simulation Results  AC-signal: 2.6V, f = 100k – 1MHz  V gs bypass: 2.5V  V mod : 1.6V  ~60mV  I mod : 3.5A  ~100mA  Control from DCS works fine V gs bp AC-signal V mod I mod I bp 39L. Gonella - TWEPP 2010 - 21/09/2010

40. Over-Voltage Protection  Silicon Controlled Rectifier  Parasitic elements (BJTs) in CMOS technologies (inverter in IO pads)  Latch-up condition: I/O voltage (U E Q1 ) > VDD  Q1 begins to conduct  Q2 switches on  Q1 draws even more current  Shorts the supply rails when triggered  That is exactly what we want! R1 M2 M1 R1 R2 M bp Local VDD Local GND module  Use MOSFETS instead of parasitic BJTs for better control of operation parameters  Trigger threshold defined by R2/R1  Want to draw high currents  R1 small  or use additional ‘power’ NMOS  bypass 40L. Gonella - TWEPP 2010 - 21/09/2010

41. SCR: Simulation Results  Sweep of R mod  V mod increases, I mod constant  The voltage across the module is effectively clamped down when the SCR activates, however  V ds bp = V gs bp  impossible to get V mod = 100mV and V gs bp = 2.5V  V mod = 850mV & I bp ≈ 3A  too high power density  The DCS should sense the OV on the module and switch on the module I bp V mod V gs bp ~850mV 41L. Gonella - TWEPP 2010 - 21/09/2010

42. HV Distribution  Use one floating HV supply per module  no problem  Use 1 HV supply per power group  several schemes possible, e.g. using the serial power line as HV return 42L. Gonella - TWEPP 2010 - 21/09/2010