1. MOSFET Structure p-Si n+ L Source Gate Drain Field Oxide Gate Oxide
Bulk (Substrate)
Structure
p-type Silicon substrate
n+ ion implanted source and drain regions
High quality (thin) gate oxide (dry process)
Overlaps slightly source and drain regions
Thick field oxide
Protection + carries contact tracks
Channel
Region between source and drain and under gate.
Enhancement Mode MOSFET
n-channel with VG>VT
Semiconductors: Si; Ge; GaAs
Insulators: SiO3; Si3N4; Al2O3
Most Important Combination: Si/SiO2
Typical Dimensions
Long channel MOSFET
L>>WS, WD
L ~ 5mm
Oxide Thickness
50-100nm

2. Importance for LSI/VLSI
Low fabrication cost
Small size
Low power consumption
Applications
Microprocessors
Memories
Power Devices
Basic Properties
Unipolar device
Very high input impedance
Capable of power gain
3/4 terminal device, G, S, D, B
Two possible device types: enhancement mode; depletion mode
Two possible channel types: n-channel; p-channel

3. Symbols G D S B G D S B
p Channel MOSFET
n Channel MOSFET

4. Current-Voltage CharacteristicB C D
IDS
VDS
Analysis
MOSFET IV Characteristics {IDS, VGS, VDS}
Simplifications
Source and bulk are grounded
Channel mobility is less than substrate mobility
Increased carrier scattering at surface!
Assume
Distinctive Regions of Characteristic
A: Low VDS
B: Intermediate VDS
C: Large VDS
D: Very Large VDS

5. Channel Formation p-Si B VG +VDS n-Channel S D
A Low Drain Source Voltage
VDS produces potential gradient in the channel
0 at source; VDS at drain
Weakens inversion in going from source to drain
However, if VDS is small then this gradient will be much smaller than the one in the perpendicular direction produced by the gate: [Gradual Channel Approximation]
Ignore this effect for small VDS
When VGS>VT, get inverted channel
Increasing VGS increases inversion
Conductivity increases
Depletion width saturates (dmax) in inversion
QD the depletion layer charge is unaffected
Carrier transport along the channel will be due to drift, I.e. due to VDS

6. Analysis: Low VDS (A) W is the channel width
W/L is known as the aspect ratio
For low VDS, IDS is linearly dependent on VDS.
VG-VT is constant

7. Intermediate VDS (B) Source Drain Channel VG VT VDS/2 VDS VG-channel
Must take potential gradient along the channel into account!
Gives rise to a variation in potential between gate and substrate along the channel.
The net potential difference from the gate to the channel decreases towards the drain.
This results in a decrease in Qn along the length of the channel.

8. Increased VDS
p-Si B VG
+VDS
n-Channel S D

9. Analysis: Intermediate VDS
First Order Approximation
Gate to Channel Voltage = VGS-VDS/2
A first approximation assumes that the gate to channel voltage is VGS-VDS/2
Extra term!

10. Large VDS: Saturation (C)
Source
Drain
Channel VG VT
VDS
VG-channel
Pinch-off
Let VDS=VG-VT = VDS(sat)
Now the gate to channel voltage at the drain end is just sufficient to bring the channel there back to the point of inversion threshold.
There will be negligible free electron charge at the drain end.
The channel pinches off.
Current saturates or increases only slightly as the pinch-off region moves towards the source.

11. Analysis: Saturation (C)
Pinch-off
Substitute for VDS(sat) in equation for IDS to get IDS(sat)
As VDS increases above VDS(sat) two effects result:
The channel length decreases.
This would cause IDS to increase slightly.
Depletion width increases.
Increases resistance to current flow.
Current should decrease.
However, excess voltage [VDS-VDS(sat)] is dropped across the depletion region and compensates for the increased resistance.

12. Avalanche and Punch-Through (D)
For very large VDS, IDS increases rapidly due to drain junction avalanche.
Can give rise to parasitic bipolar action.
In short channel transistors, the drain depletion region may reach the source depletion region giving rise to ‘Punch Through’.