1. Technology Development for InGaAs/InP-channel MOSFETs
MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco
Technology Development for InGaAs/InP-channel MOSFETs
Mark Rodwell University of California, Santa Barbara
, fax

2. Scope of Presentation
Topic of discussion is channel materials for CMOS ...the potential use of III-V materials ...and their advantages and limitations
To understand this, we must examine in some detail MOSFET scaling limits

3. Zeroth-Order MOSFET Operation

4. Bipolar Transistor ~ MOSFET Below Threshold

5. Field-Effect Transistor Operation
source
drain
gate
Positive Gate Voltage
→ reduced energy barrier
→ increased drain current

6. FETs: Computing Their Characteristics

7. FET Characteristics

8. FET Subthreshold Characteristics

9. Classical Long-Channel MOSFET Theory

10. Classic Long-Channel MOSFET Theory
constant-current
mobility-limited
Ohmic
velocity-limited

11. Classic Long-Channel FET : Far Above Threshold

12. Exponential, Square-Law, Linear FET Characteristics

13. Relevance of DC Parameters
Digital circuit speed largely controlled by on-state current
Standby power consumption controlled by off-state current
Dynamic power consumption controlled by supply Voltage
→ Examine VLSI Power & Delay Relationships

14. Zeroth-Order VLSI Performance Analysis

15. CMOS Power Dissipation & Gate Delay

16. Why Large Current Density is Needed

17. Device Requirements High on-state current per unit gate width
Low off-state current→ subthreshold slope
Low device capacitance; but only to point where wires dominate
Low supply voltage: probably 0.5 to 0.7 V

18. What Are Our Goals ?
Low off-state current (10 nA/mm) for low static dissipation → good subthreshold slope → minimum Lg / Tox low gate tunneling, low band-band tunneling
Low delay CFET DV/I d in gates where
transistor capacitances dominate.
~1 fF/mm parasitic capacitances
→ low Cgs is desirable, but high Id is imperative
Low delay Cwire DV/Id in gates where
wiring capacitances dominate.
large FET footprint → long wires between gates → need high Id / Wg ; target ~5 DV= 0.7V target ~ 3 DV= 0.5V

19. Improving FETs
by Scaling

20. Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays → keep constant all resistances, voltages, currents
Simple FET Scaling
All lengths, widths, thicknesses reduced 2:1
S/D contact resistivity reduced 4:1
If Tox cannot scale with gate length, Cparasitic / Cgs increases, gm / Wg does not increase hence Cparasitic /gm does not scale

21. FET scaling: Output Conductance & DIBL
transconductance
output conductance
→ Keep Lg / Tox constant as we scale Lg

22. FET Scaling Laws Changes required to double transistor bandwidth:
parameter
change
gate length
decrease 2:1
gate dielectric capacitance density
increase 2:1
gate dielectric equivalent thickness
channel electron density
source & drain contact resistance
decrease 4:1
current density (mA/mm)

23. nm Transistors: it's all about the interfaces
Metal-semiconductor interfaces (Ohmic contacts): very low resistivity
Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density
Transistor & IC thermal resistivity.

24. FET Scaling Laws
Changes required to double transistor bandwidth:
parameter
change
gate length
decrease 2:1
gate dielectric capacitance density
increase 2:1
gate dielectric equivalent thickness
channel electron density
source & drain contact resistance
decrease 4:1
current density (mA/mm)
What do we do if gate dielectric cannot be further scaled ?

25. Why Consider MOSFETs with III-V Channels ?
If FETs cannot be further scaled, instead increase electron velocity:
Id / Wg = qnsv Id / Qtransit = v / Lg
III-V materials → lower m*→ higher velocity
( need > 1000 cm2 /V-s mobility)
Candidate materials (?) InxGa1-xAs, InP, InAs ( InSb, GaAs)
Difficulties: High-K dielectrics III-V growth on Si building MOSFETs low m* constrains vertical scaling, reduces drive current

26. III-V CMOS: The Benefit Is Low Mass, Not High Mobility
low effective mass → high currents
mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg

27. III-V MOSFETs for VLSI What is it ? MOSFET with an InGaAs channel
Why do it ? low electron effective mass→ higher electron velocity
more current, less charge at a given insulator thickness & gate length very low access resistance
What are the problems ? low electron effective mass→ constraints on scaling ! must grow high-K on InGaAs, must grow InGaAs on Si
Device characteristics must be considered in more detail

28. III-V MOSFET
Characteristics

29. Low Effective Mass Impairs Vertical Scaling
Shallow electron distribution needed for high gm / Gds ratio, low drain-induced barrier lowering.
Energy of Lth well state
For thin wells,
only 1st state can be populated.
For very thin wells,
1st state approaches L-valley.
Only one vertical state in well. Minimum ~ 5 nm well thickness.
→ Hard to scale below 22 nm Lg.

30. Semiconductor (Wavefunction Depth) Capacitance

31. Density-Of-States Capacitance
and n is the # of band minima
Two implications:
- With Ns >1013/cm2, electrons populate satellite valleys
- Transconductance dominated by finite state density
Fischetti et al, IEDM2007
Solomon & Laux , IEDM2001

32. Current Including Density of States, Wavefunction Depth
...but with III-V materials, we must also consider degenerate carrier concentrations.

33. Current of Degenerate & Ballistic FET

34. 2D vs. 1D Field-Effect Transistors in Ballistic Limit

35. 2D FET vs. Carbon Nanotube FET

36. Ballistic/Degenerate Drive Current vs. Gate Voltage
More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007

37. Drive Current in the Ballistic & Degenerate Limits
Error bars on Si data points correct for (Ef-Ec)>> kT approximation
n = # band minima cdos,o = density of states capacitance for m*=mo & n=1

38. High Drive Current Requires Low Access Resistance

39. What channel material should we use ?
Materials Selection;
What channel material should we use ?

41. Common III-V Semiconductors
B. Brar
InAs
360
GaSb
770
AlSb
1550
GaAs
1420
InGaAs
760
InAlAs
1460
InP
1350
200
500
450
250
550
170
InGaP
1900
InSb
220
150
AlAs
2170
6.48 A lattice constant
6.48 A lattice constant
5.65 A lattice constant; grown on GaAs
5.87 A lattice constant; grown on InP

42. Semiconductor & Metal Band Alignments
M. Wistey

43. Materials of Interest material Si Ge GaAs InP In0.53Ga0.47As InAs
Source: Ioffe Institute rough #s only
material Si Ge GaAs InP In0.53Ga0.47As InAs n
m*/m ml 1.6 ml
0.19 mt mt
G-(L/X) separation, eV ~
bandgap, eV
mobility, cm2/V-s , ,000
high-field velocity 1E7 1E7 1-2E7 3.5E7 3.5E7 ???

44. Drive Current in the Ballistic & Degenerate Limits
Error bars on Si data points correct for (Ef-Ec)>> kT approximation Ge
n = # band minima cdos,o = density of states capacitance for m*=mo & n=1 Si
InGaAs
InP

45. Intervalley Separation
Source: Ioffe Institute
Intervalley Separation
Intervalley separation sets:
-high-field velocity through intervalley scattering
-maximum electron density in channel without increased carrier effective mass

46. Choosing Channel Material: Other Considerations
Ge: low bandgap
GaAs: low intervalley separation
InP: good intervalley separation Good contacts only via InGaAs→ band offsets moderate mass→ better vertical scaling
InGaAs good intervalley separation bandgap too low ? → quantization low mass→ high well energy→ poor vertical scaling
InAs: good intervalley separation bandgap too low
very low mass→ high well energy→ poor vertical scaling

47. Non-Parabolic Bands

48. Non-Parabolic Bands
T. Ishibashi, IEEE Transactions on Electron Devices, 48,11 , Nov. 2001,

49. MOSFET Design Assuming In0.5Ga0.5As Channel

50. Device Design / Fabrication Goals
gate overdrive mV drive current mA/mm Ns 6* * * /cm2 Dielectric: EOT 0.6 nm target, ~1.5 nm short term
Channel : nm thick m > nm, 6*1012 /cm2
S/D access resistance: W-mm resistivity→ 0.5 W-mm2 contacts , ~2*1013 /cm2 , ~4*1019 /cm3 , 5 nm depth

51. Target Device Parameters

52. Device Structure &
Process Flow

53. Device Fabrication: Goals & Challenges
Source
Drain
Gate
III-V HEMTs are built like this→
K Shinohara
....and most III-V MOSFETs are built like this→

54. Device Fabrication: Goals & Challenges
Yet, we are developing, at great effort, a structure like this →
Why ?
Source
Drain
Gate
K Shinohara

55. Why not just build HEMTs ? Gate Barrier is Low !
Gate barrier is low: ~0.6 eV
Source
Drain
Gate
K Shinohara
Tunneling through barrier → sets minimum thickness
Emission over barrier → limits 2D carrier density

56. Why not just build HEMTs ?
Gate barrier also lies under source / drain contacts
Source
Drain
Gate
N+ layer
widegap barrier layer
K Shinohara
low leakage: need high barrier under gate
low resistance: need low barrier under contacts

57. How do we make this device ?
The Structure We Need
-- is Much Like a Si MOSFET
no gate barrier under S/D contacts
high-K gate barrier
Overlap between gate and N+ source/drain
How do we make this device ?

58. S/D Regrowth Process Flow

59. Regrown S/D FETs: Versions
Wistey et al MBE conference
Regrown S/D FETs: Versions
regrowth under sidewalls
planar regrowth
need thin sidewalls (now ~20-30 nm)
..or doping under sidewalls

60. S/D Regrowth by Migration-Enhanced Epitaxy
Wistey et al MBE conference
MBE growth is line-of-sight → gaps in regrowth near gate edges
MEE provides surface migration during regrowth→ eliminates gaps
SEM Cross Section
SEM Side View (Oblique)
Top of gate
SiO2 dummy gate
SiO2 dummy gate
Side of gate
InGaAs Regrowth
InGaAs Regrowth
Original Interface
SEM: Greg Burek
SEM: Uttam Singisetti
No gaps
Smooth surfaces.
High Si activation (4x1019 cm-3).
Quasi-selective: no growth on sidewalls

61. Self-Aligned Planar III-V MOSFETs by Regrowth
Wistey Singisetti Burek Lee
Self-Aligned Planar III-V MOSFETs by Regrowth
N+ InGaAs regrowth, Mo contact metal
gate
Mo contact metal

62. Self-Aligned Planar III-V MOSFETs by Regrowth
Wistey Singisetti Burek Lee
Self-Aligned Planar III-V MOSFETs by Regrowth

63. Regrown S/D FETs: Images

64. Regrown S/D FETs: Images

65. III-V MOS

66. InGaAs / InP MOSFETs: Why and Why Not
low m*/m0 → high vcarrier → more current
low m*/m0 → low density of states → less current
ballistic / degenerate calculation
Error bars on Si data points correct for (Ef-Ec)>> kT approximation
n = # band minima cdos,o = density of states capacitance for m*=mo & n=1
Low m* impairs vertical (hence Lg ) scaling ; InGaAs no good below 22-nm.
InGaAs allows very low access resistance
Si wins if high-K scales below 0.6 nm EOT; otherwise, III-V has a chance

67. InGaAs/InP Channel MOSFETs for VLSI
Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm
Devices cannot scale much below 22 nm Lg→ limits IC density
Little CV/I benefit in gate lengths below 22 nm Lg
Need device structure with very low access resistance
radical re-work of device structure & process flow
Gate dielectrics, III-V growth on Si: also under intensive development