1. MALVINO
Electronic
PRINCIPLES
SIXTH EDITION

2. MOSFETs
Chapter 14

3. Depletion-mode MOSFET
Metal
oxide
insulator n
Source
Gate
Drain
VDD
VGG p
Drain n
VDD
Gate p
VGG
Source
(depletion mode)
(enhancement mode)
Since the gate is insulated, this device can
also be operated in the enhancement mode.

4. MOSFETs
Current flows through a narrow channel between the gate and substrate.
SiO2 insulates the gate from the channel.
Depletion mode forces the carriers from the channel.
Enhancement mode attracts carriers into the channel.
E-MOSFETs are normally-off devices.

5. n-channel E-MOSFET Drain n D VDD Gate p G n S VGG Source
Gate bias enhances the channel and turns the device on.

6. n-channel E-MOSFET
The p-substrate extends all the way to the silicon dioxide.
No n-channel exists between the source and drain.
This transistor is normally off when the gate voltage is zero.
A positive gate voltage attracts electrons into the p-region to create an n-type inversion layer and turns the device on.

7. p-channel E-MOSFET Drain p D VDD Gate n G p S VGG Source
Gate bias enhances the channel and turns the device on.

8. p-channel E-MOSFET
The n-substrate extends all the way to the silicon dioxide.
No p-channel exists between the source and drain.
This transistor is normally off when the gate voltage is zero.
A negative gate voltage attracts holes into the n-region to create an p-type inversion layer and turns the device on.

9. n-channel E-MOSFET drain curves
Ohmic region
Constant current region ID
+10 V
+5 V
VGS(th)
VDS

10. n-channel E-MOSFET transconductance curveID
Ohmic
ID(sat)
Active
VGS
VGS(th)
VGS(on)

11. Gate breakdown The SiO2 insulating layer is very thin.
It is easily destroyed by excessive gate-source voltage.
VGS(max) ratings are typically in tens of volts.
Circuit transients and static discharges can cause damage.
Some devices have built-in gate protection.

12. Drain-source on resistance
VGS = VGS(on)
Qtest
ID(on)
VDS(on)
ID(on)
RDS(on) =
VDS(on)

13. Biasing in the ohmic region
VGS = VGS(on)
+VDD
Qtest
ID(on)
ID(sat) RD Q
VGS
VDD
ID(sat) < ID(on) when VGS = VGS(on) ensures saturation

14. Passive and active loads
+VDD
+VDD RD Q1
vout
vout Q2
vin
vin
Passive load
Active load
(for Q1, VGS = VDS)

15. VGS = VDS produces a two-terminal curveID
VGS
+5 V
5 V
10 V
15 V
VDS

16. Active loading in a digital inverter
+VDD
VDS(active)
ID(active)
RDQ1 = Q1
0 V
+VDD
vout
0 V
+VDD Q2
vin
It’s desirable that RDSQ2(on) << RDQ1.
(The ideal output swings from 0 volts to +VDD.)

17. Complementary MOS (CMOS) inverter
+VDD
Q1 (p-channel)
0 V
+VDD
0 V
+VDD
vin
vout
Q2 (n-channel)
PD(static) @ 0

18. CMOS inverter input-output graph
vout
VDD
VDD 2
Crossover point
PD(dynamic) > 0
vin
VDD 2
VDD

19. High-power EMOS Use different channel geometries to extend ratings
Brand names such as VMOS, TMOS and hexFET
No thermal runaway
Can operate in parallel without current hogging
Faster switching due to no minority carriers

20. dc-to-ac converter
vac
Power
FET
+VGS(on)
0 V

21. dc-to-dc converter
vdc
Power
FET
+VGS(on)
0 V