1. Dynamic Data Stability in Low-power SRAM Design Mohammad Sharifkhani, Shah M. Jahinuzzaman and Manoj Sachdev Electrical & Computer Engineering University of Waterloo, Waterloo, ON, Canada

2. 2 Background Static Noise Margin (SNM) is based on –static criteria –worst case static noise

3. 3 Analysis of non-linear system by state-space –differential equations –discontinuity of MOS I/V characteristics: use of subthreshold operation for continuity Different sets of eq. for accessed and non- accessed modes SRAM Cell: Non-linear System

4. 4 Non-linear system –multiple stable or DC points region of convergence –time domain solutions relies on initial conditions trajectories While non-accessed – 2 Uniformly Asymptotic Stable (UAS) points – 1 saddle point State-space Analysis of Cell No discontinuity in state variable V – finite admittance of access transistors

5. 5 Shadow of the ball on 2D state space: trajectory 3 stable points Final DC solution depends on initial location of the ball Analogy with Saddle

6. 6 Data unstablity: state of cell moves away from the RoC of the original UAS point determined in non-accessed mode –occurs if the accessed cell has only one UAS point that resides out of the original RoC Data Unstability in SRAM Cell

7. 7 State of cell never leaves the RoC of original logic state –existence of a periodic solution for the PTV-NL cell within each RoC of UAS point Worst case scenario: infinite access transactions Dynamic Data Stability Criteria

8. 8 The periodic solutions are convergent –don’t have to solve the PTV-NL for all initial conditions (despite being a nonlinear system) –the solution will attract the trajectory, if exists –the initial condition should be in the RoC of periodic solution Proof: beyond the scope of this presentation Properties of Trajectories

9. 9 SNM redefined as SNM D : same noise sources, but dynamic criteria In subthreshold region, lower cell access time results in higher SNM D Static Noise Margin using Dynamic Criteria

10. 10 Segmented Virtual Grounding (SVGND) scheme is proposed –low-leakage –low-write power higher write NM –low excess power on non-selected BL –minor speed trade-off –four distinct operational modes 1. Retention2. Read 3. Accessed retention4. Write Application in Low-power SRAM

11. 11 Array is in hibernation V H – V L = 0.4V No multiple V T s! Body effect minimizes leakage Potential issue: data stability –weak drive transistors Retention Mode

12. 12 Simulation & Measurement Results Measurement results –Leakage current reduces significantly Stability simulation results –SNM (220mV) Sub-threshold operation (~22pA/Cell)

13. 13 Multiple words/row Only selected word enters this mode –SVG becomes VSS –bitline discharges via access & driver transistors Good data stability –voltage across cell ≈ V H –V B -V A > V H -V L Read Mode

14. 14 Non-selected words (BLs) on selected row enters this mode –high V WL –no SVG variation –no bitline discharge Minimum access leakage Issue: data stability –V wl = V H +V tha -V Δ –V Δ > 200mV –recovery after access Accessed Retention Mode

15. 15 Low BL voltage swing –V WR Sufficiently below V H -V Δ –V WR = V L –BL swing,  V BL ≈ 400 mV Low power consumption –P write ∝ V H.  V BL –no SVG variation Write Mode

16. 16 SVGND Architecture Constitute the OP modes Small area overhead Column based –Sharing SVG Nominal V L, access V cvg SS / WL : simultaneous –Connection to CVG –Sharing CVG High metal layer (low cap) Nominal V L, read V SS

17. 17 SVGND Architecture

18. 18 SVGND Architecture Post Dec: AND No additional HW for SS CVG and BL voltage variation: –Only to-be-read columns –Others: AR- mode

19. 19 Comparison: Write

20. 20 Simulated Waveforms

21. 21 Silicon Implementation Array size: 2048x20bit 130nm CMOS 4 arrays –Each 150um x 410um 8% area overhead F clk >50MHz

22. 22 SVGND Meas. Results Normalized voltage & freq. Less area overhead compared to JSSC’04(11%) and ISSCC’06(66%) and JSSC’05(18%) Ability to accommodate Multiple words/row