1. UC Berkeley, Dept of EECS EE141, Fall 2005, Project 2 Speed/Area Optimized 8-bit Adder Design Name 1 Name 2 Delay(  s) ·Area(  m 2 ) = {your number}

2. EE141 – Project 22 Design Summary  Adder topology, Circuit Style (e.g. CSA, static CMOS)  WHY: about A, about D, other (e.g. moderate A, fast, regular design)  Corner: TT, temp=25C  If your design is dynamic, include clock tree power!  Measure power over 20ns using test vectors from pg.5 (SCH) t p (ns) = A (  m 2 ) = (LAY) t p (ns) =Aspect ratio = # gates on crit path = LAY t p *A (  s*  m 2 ) = (LAY) P (100MHz) =Passed LVS: Yes No (report the numbers with 3 decimal places)

3. EE141 – Project 23 Critical Path Analysis  Input transition for critical path  Highlight critical path  block diagram of design  indicate critical transition  write down critical path equation

4. EE141 – Project 24 Sizing Optimization  illustration of gate level critical path  MOS transistor detail of critical gates  sizing numbers of the critical gates

5. EE141 – Project 25 Functionality Check  Input vectors (MSB-to-LSB): A = 00000000  10110110  00101001 B = 00000000  01011011  01010110 C in = 0  1  1  plot S 0 -S 7 & C out on three graphs (each bit has its own plot) for the above transition vectors Format: see table (table should span whole page) X-axis = 20ns range −Last 5ns of the first vector −Full 10ns for the second −First 5ns of the last vector S0S0 S3S3 S6S6 S1S1 S4S4 S7S7 S2S2 S5S5 C out

6. EE141 – Project 26 Layout Techniques  show layout floorplan (indicate the location of main adder building blocks)  use Cadence ruler to clearly indicate size in  m  highlight critical path in your layout  aspect ratio has to be < 1.5  pins must be on the top-level cell boundary  label the pins in your layout