1. Slide 4-1 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 4 Computer Organization

2. Slide 4-2 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 CSCI 3753 Announcements Moodle - posted last Tuesday’s lecture Programming shell assignment 0 due Thursday at 11:55 pm, not 11 am Homework #1 due next Thursday at 11 am Read Chapters 3 and 4 in the textbook, skip 4.7 and 4.8

3. Slide 4-3 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Stored Program Computers and Electronic Devices Patter n Fixed Electronic Device Variable Program Stored Program Device Jacquard Loom

4. Slide 4-4 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Program Specification int a, b, c, d;... a = b + c; d = a - 100; Source ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Assembly Language

5. Slide 4-5 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Machine Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Assembly Language 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 10111001010000…0 10100110001100…0 10111001101100…1 Machine Language

6. Slide 4-6 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The von Neumann Architecture Control Unit (CU) Central Processing Unit (CPU) Device Address Bus Data Bus Arithmetical Logical Unit (ALU) Primary Memory Unit (Executable Memory)

7. Slide 4-7 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The ALU R1 R2 Rn... Status Registers Functional Unit Left Operand Right Operand Result To/from Primary Memory load R3,b load R4,c add R3,R4 store R3,a

8. Slide 4-8 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit 3046 3050 3054 3058 Primary Memory Fetch Unit Decode Unit Execute Unit PC IR Control Unit load R3,b load R4,c add R3,R4 store R3,a 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 load R4, c 3050

9. Slide 4-9 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit Operation PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase }; Fetch phase: Instruction retrieved from memory Execute phase: ALU op, memory data reference, I/O, etc.

10. Slide 4-10 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Primary Memory Unit MAR MDR Command 0 1 2 n-1 123498765 Read Op: 1234 1. Load MAR with address read 2. Load Command with “read” 98765 3. Data will then appear in the MDR

11. Slide 4-11 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Processor Modes Mode bit: Supervisor or User mode Supervisor mode –Can execute all machine instructions –Can reference all memory locations User mode –Can only execute a subset of instructions –Can only reference a subset of memory locations

12. Slide 4-12 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Kernels The part of the OS critical to correct operation (trusted software) Executes in supervisor mode The trap instruction is used to switch from user to supervisor mode, entering the OS

13. Slide 4-13 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Supervisor and User Memory User Space User Space Supervisor Space Supervisor Space User Process User Process Supervisor Process Supervisor Process

14. Slide 4-14 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Procedure Call and Message Passing Operating Systems call(…); trap return; send(…, A, …); receive(…, B, …); receive(…A, …); … send(…, B, …); send/receive

15. Slide 4-15 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 System Call Using the trap Instruction … fork(); … fork() { … trapN_SYS_FORK() … } sys_fork() sys_fork() { /* system function */ … return; } Kernel Trap Table

16. Slide 4-16 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 A Thread Performing a System Call User SpaceKernel Space fork(); sys_fork() { } Thread

17. Slide 4-17 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Examples of Exceptions in Pentium Systems ClassCauseAsync/ Sync Return behavior TrapIntentional exception Syncalways returns to next instruction FaultPotentially recoverable error Syncmight return to current instruction Abortnonrecover- able error Syncnever returns Interruptsignal from I/O device Asyncalways returns to next instruction

18. Slide 4-18 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Examples of Exceptions Kinds of Exceptions –traps, e.g. system calls –interrupts –faults –aborts Pentium: Table of 256 different exception types –some assigned by CPU designers (divide by zero, memory access violations, page faults) –some assigned by OS, e.g. system calls Pentium CPU contains exception table base register that points to this table

19. Slide 4-19 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Examples of Exceptions in Pentium Systems Exception Number DescriptionException Class 0Divide errorfault 13General protection fault fault 14Page faultfault 18machine checkabort 32-127OS-definedInterrupt or trap 128System callTrap 129-255OS-definedInterrupt or trap Exception Table OS assigns

20. Slide 4-20 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The Device-Controller-Software Relationship Application Program Device Controller Device Software in the CPU Abstract I/O Machine Device manager Program to manage device controller Supervisor mode software

21. Slide 4-21 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Device Controller Interface Command Status Data 0 Data 1 Data n-1 Logic busydoneError code... busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)

22. Slide 4-22 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Performing a Write Operation while(deviceNo.busy || deviceNo.done) ; deviceNo.data[0] = deviceNo.command = WRITE; while(deviceNo.busy) ; deviceNo.done = TRUE; Devices much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while I/O is in process

23. Slide 4-23 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 CPU-I/O Overlap CPU Device … Ready Processes CPU Device … Ready Processes I/O Operation CPU Device … Ready Processes Uses CPU

24. Slide 4-24 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Polling I/O - Busy Waiting … // Start the device … While((busy == 1) || (done == 1)) wait(); // Device I/O complete … done = 0; … while((busy == 0) && (done == 1)) wait(); // Do the I/O operation busy = 1; … busydone Software Hardware

25. Slide 4-25 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Determining When I/O is Complete CPU Device Interrupt Pending CPU incorporates an “interrupt pending” flag When device.busy  FALSE, interrupt pending flag is set Hardware “tells” OS that the interrupt occurred Interrupt handler part of the OS makes process ready to run

26. Slide 4-26 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit with Interrupt (Hardware) PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1] }; memory[1] contains the address of the interrupt handler

27. Slide 4-27 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Interrupt Handler (Software) interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */ deviceHandler(int i) { finishOperation(); returnToScheduler(); }

28. Slide 4-28 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 A Race Condition saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+NumberOfRegisters+i] = StatusRegister[i]; } PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest && InterruptEnabled) { disableInterupts(); memory[0] = PC; PC = memory[1] };

29. Slide 4-29 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Revisiting the trap Instruction (Hardware) executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2... case n: PC = memory[1000+n];// Trap handler n }; The trap instruction dispatches a trap handler routine atomically Trap handler performs desired processing “A trap is a software interrupt”

30. Slide 4-30 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The Trap Instruction Operation S Mode Trusted Code trap UserSupervisor Branch Table 2 31

31. Slide 4-31 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Direct Memory Access Primary Memory CPU Controller Device Primary Memory CPU Controller Device

32. Slide 4-32 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Memory-Mapped I/O: Addressing Devices Primary Memory Device 0 Device 1 Device n-1 Primary Memory Device 0 Device 1 Device n-1 Device Addresses Memory Addresses Memory-Mapped Addresses No need for special instructions to access a device MMU takes care of the mapping

33. Slide 4-33 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Intel System Initialization ROM CMOS RAM Boot Device POST BIOS Boot Prog Loader OS … Hardware Process Data Flow Power Up

34. Slide 4-34 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Bootstrapping Bootstrap loader (“boot sector”) Primary Memory 1 0x0001000 Fetch Unit Decode Unit Execute Unit 0000100 … … PC IR BIOS loader 0x0000100

35. Slide 4-35 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Bootstrapping Bootstrap loader (“boot sector”) Primary Memory Loader 1 2 Fetch Unit Decode Unit Execute Unit 0001000 … … PC IR BIOS loader 0x0000100 0x0001000 0x0008000

36. Slide 4-36 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Bootstrapping Bootstrap loader (“boot sector”) Primary Memory Loader OS 1 2 3 Fetch Unit Decode Unit Execute Unit 0008000 … … PC IR BIOS loader 0x0000100 0x0001000 0x0008000 0x000A000

37. Slide 4-37 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Bootstrapping Bootstrap loader (“boot sector”) Primary Memory Loader OS 1 2 3 4. Initialize hardware 5. Create user environment 6. … Fetch Unit Decode Unit Execute Unit 000A000 … … PC IR BIOS loader 0x0000100 0x0001000 0x0008000 0x000A000

38. Slide 4-38 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 A Bootstrap Loader Program FIXED_LOC: // Bootstrap loader entry point loadR1, =0 loadR2, =LENGTH_OF_TARGET // The next instruction is really more like // a procedure call than a machine instruction // It copies a block from FIXED_DISK_ADDRESS // to BUFFER_ADDRESS readBOOT_DISK, BUFFER_ADDRESS loop:loadR3, [BUFFER_ADDRESS, R1] storeR3, [FIXED_DEST, R1] incrR1 bleqR1, R2, loop brFIXED_DEST