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Published byEmily Tyler Modified over 9 years ago
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Error/Flow Control Modeling (ARQ Modeling)
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© Tallal Elshabrawy 2 Data Link Layer Data Link Layer provides a service for Network Layer (transfer of data from the network layer of a sender to the network layer of a receiver) Data Link Layer uses the Physical Layer to transmit bits of Data Link Frames over the physical medium LLC MAC Network Physical
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© Tallal Elshabrawy 3 Data Link Layer Functions Framing (Grouping Bits into Frames) Error Control Flow Control Medium Access Control
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© Tallal Elshabrawy 4 Bit Errors in Communication Systems At the physical layer, bit errors are inevitable to occur with small but non zero probability, example: Bit error probability in the order of 10 -6 for systems using copper wires Bit error probability in the order of 10 -9 for modern optical fiber systems High bit error probability in the order of 10 -3 for wireless transmission systems Some services are tolerant to relatively high bit error rates such as digital speech transmission Some applications must experience error-free communications such as electronic funds transfer
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© Tallal Elshabrawy 5 Error Control Error Control is a system to deal with errors that occur due to disturbances on the physical channel. Components of an error control system: Error Correction and Detection Acknowledgement (ACK) & Non- Acknowledgement Control Messages (NAK) Timers Sender Receiver 0 0 Data Frame ACK No Errors 1 1 Errors 1 1 ACK No Errors Timer Frame is Good Detection/ Correction Detection/ Correction Detection/ Correction
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© Tallal Elshabrawy 6 Error Control Mechanisms Forward Error Correction (FEC) Detection of erroneous frames or packets Processing of received frame bits in attempt to correct the errors Automatic Retransmission reQuest (ARQ) Detection of erroneous frames or packets Retransmission of erroneous frames with the hope that no errors would occur in the next attempt
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© Tallal Elshabrawy 7 Automatic Repeat reQuest (ARQ) Protocols Purpose: to ensure a sequence of information packets is delivered in order and without errors or duplications despite transmission errors & losses (Error Control & Flow Control)
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Modeling of Stop and Wait Protocol
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© Tallal Elshabrawy 9 Stop-and-Wait ARQ Stop after Transmitting a Packet Wait for an Acknowledgement H: Header CRC: Cyclic Redundancy Check (Error Detection)
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© Tallal Elshabrawy 10 Stop-and-Wait ARQ Operation Machine A Machine B Physical Channel First Packet-Bit enters Channels Last Packet-Bit enters Channels First Packet-Bit arrives at B Last Packet-Bit arrives at B Last ACK-Bit Arrives at A Processing Time for Error Detection Channel is Idle
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© Tallal Elshabrawy 11 Stop-and-Wait ARQ Operation Machine A Machine B Physical Channel
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© Tallal Elshabrawy Stop-and-Wait ARQ Modeling 12 Machine A Machine B Physical Channel
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© Tallal Elshabrawy Stop-and-Wait ARQ Markov Model 13
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© Tallal Elshabrawy Stop-and-Wait ARQ Markov Model 14
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© Tallal Elshabrawy Stop-and-Wait ARQ Performance 15
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© Tallal Elshabrawy Stop-and-Wait ARQ Efficiency 16 Efficiency Decreases with: Increase in BER Increase in Packet Size
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© Tallal Elshabrawy Stop-and-Wait ARQ Throughput 17 Notes Throughput does not care how many attempts have been done to successfully transmit a packet Throughput measures the channel utilization for successful transmission Efficiency rather measures the delay of a given packet Both efficiency and throughput represent two faces of the same coin
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© Tallal Elshabrawy Stop-and-Wait ARQ Simplified Model 18
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