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Pico-Sec Simulation Workshop University of Chicago 12/12/06 Simulating Front-end Electronics and Integration with End-to-end Simulation Fukun Tang Enrico.

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Presentation on theme: "Pico-Sec Simulation Workshop University of Chicago 12/12/06 Simulating Front-end Electronics and Integration with End-to-end Simulation Fukun Tang Enrico."— Presentation transcript:

1 Pico-Sec Simulation Workshop University of Chicago 12/12/06 Simulating Front-end Electronics and Integration with End-to-end Simulation Fukun Tang Enrico Fermi Institute University of Chicago With Karen Byrum and Gary Drake (ANL) Henry Frisch, Mary Heintz and Harold Sanders (UC)

2 Pico-Sec Simulation Workshop University of Chicago 12/12/06 Harold’s TOF System dum

3 Time Stretcher TDC psFront-end Start Stop 500pS Tw MCP_PMT Output Signal Reference Clock “fine” time interval

4 IBM SiGe BiCMOS 8HP Process 130-nm Technology 130-nm Technology SiGe Hetero-junction Bipolar Transistors SiGe Hetero-junction Bipolar Transistors f T (high performance): 200GHz, BVceo=1.7V, BVcbo=5.9V f T (high performance): 200GHz, BVceo=1.7V, BVcbo=5.9V f T (high breakdown): 57GHz, BVceo=3.55V, BVcbo=12V f T (high breakdown): 57GHz, BVceo=3.55V, BVcbo=12V High-Q Inductors and Metal-Isolator-Metal Capacitors High-Q Inductors and Metal-Isolator-Metal Capacitors 4 Types of Low-tolerance Resistors with Low and High Sheet Resistivity 4 Types of Low-tolerance Resistors with Low and High Sheet Resistivity n+ Diffusion, Tantalum Nitride, p+ Polisilicon and p- Polisilicon n+ Diffusion, Tantalum Nitride, p+ Polisilicon and p- Polisilicon Electrically Writable e-Fuse Electrically Writable e-Fuse CMOS Transistors (VDD=1.2V or 2.5/3.3V) CMOS Transistors (VDD=1.2V or 2.5/3.3V) Twin-well CMOS Twin-well CMOS Hyperabrupt Junction and MOS Varactors Hyperabrupt Junction and MOS Varactors Deep Trench and Shallow Trench Isolations Deep Trench and Shallow Trench Isolations 3 to 5 Copper Layers and 2 Aluminum Layers (up to 3 thick layers) 3 to 5 Copper Layers and 2 Aluminum Layers (up to 3 thick layers) Wire-bond or Controlled Collapse Chip Connect (C4) Solder-bump Terminals Wire-bond or Controlled Collapse Chip Connect (C4) Solder-bump Terminals

5 Cadence Custom IC Design Flow for IBM 8HP Design Specification Virtuoso Schematic Analog Design Environment (ADE) AMS Design Environment (AMS) Virtuoso XL Layout Chip Assembly Router Assura DRC/LVC, RCX Schematic Capture Circuit Simulations Cell/Chip Layout Verification and RF Parasitic Extraction ADE, AMS Simulations Post-Layout Simulations Mask Generation GDSII Stream Out DRC, Filler Generation Validation Tape-Out IBM 8HP PDK Library, tech files Models Tech File, DRC, PCell Tech File, DRC Models, RCX Tech File Tech, Foundry Rules

6 Interface to Other Simulation Tools ASCII files: Waveform time-value pair Tube Output Signals from Simulation Tube Output Signals from Scope System Simulation Results IBM 8HP PDK Cadence Virtuoso Analog Environment Or Cadence Virtuoso AMS Environment Custom Chip Schematic Spectre Netlist (Cadence Spice) ASCII files: Waveform time-value pair Spectre Netlist Spectre Library Cadence Simulator

7 Waveform Time-value Pair Format

8 02/2007 MOSIS Submission (2GHz VCO) 2GHz VCO Schematics Simplified VCO Core Schematic SiGe HJT, negative resistance differential VCO On-chip high-Q LC tank High Frequency PN diode Varactors Capacitor voltage dividers 50-ohm line drivers

9 VCO Simulation Result V-F Transfer Function Tuning Range=7.5% Output Waveforms Phase Noise -97dBc/Hz Equivalents to Cycle-to- cycle time-jitter of 5 fs

10 Pico-Sec Simulation Workshop University of Chicago 12/12/06Conclusion A journey of 1000 miles begins with a single step. ---Lao Tzu (Laozi), 600 B.C. We entered a completely different world than most of us live in. We have lots to learn, lots need to be done.


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