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Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.

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Presentation on theme: "Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager."— Presentation transcript:

1 Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager

2 Tools - Design Manager - Chapter 6 slide 2 Version 1.5 In this Chapter, You Will Learn How to invoke the Design Manager and set up for implementation How to implement your design in an FPGA We’ll start with a low speed, or “push-button” flow –Options for high-speed/large designs will be shown tomorrow

3 Tools - Design Manager - Chapter 6 slide 3 Version 1.5 Outline Design Flow Design Manager Implementation –Design Manager Windows –Design flow to implement the design –Checking results –Configuring or programming the FPGA Foundation Implementation Summary

4 Tools - Design Manager - Chapter 6 slide 4 Version 1.5 Introducing Xilinx Software Xilinx’ Design Manager IMPLEMENTS your design –Places and Routes your netlist to create a data file to program your FPGA or CPLD –Open Framework to major EDA Tools –Generate your netlist with common synthesis or schematic tools –Simulate with common tools such as MTI or Cadence Verilog Xilinx’ Foundation CREATES your design –Contains Synthesis, Schematic, and Simulation tools –Also contains Design Manager Use Design Manager with Foundation and/or EDA tools

5 Tools - Design Manager - Chapter 6 slide 5 Version 1.5 Alliance Software Package Alliance Software Package contains Design Manager –Use with standard EDA tools including Synopsys, Synplicity, Exemplar, MTI, Cadence, and Mentor Tools –Available on UNIX or PC Schematic, Cores HDL Code Design Implementation Static Timing Analysis, In-Circuit Testing Design Manager Functional Simulation Design Iteration Third Party Simulation Functional and Timing VHDL, Verilog or Gate Level Third Party Design Entry Synthesis or Schematic

6 Tools - Design Manager - Chapter 6 slide 6 Version 1.5 Xilinx EDA Alliance A team effort between Xilinx and EDA vendors to simplify and shorten the ASIC design cycle. Major Design Entry and Simulation vendors: –Cadence, Mentor Graphics, Viewlogic, Model Technologies, OrCad –Synopsys, Synplicity, Synario, Exemplar, ABEL, Aldec Support of industry standard file formats –VHDL, Verilog, and EDIF netlist formats –SDF Standard Delay file –VITAL library support Current lists of Alliance Members, supported products, and contacts are available on the Xilinx WEB site –From www.xilinx.com -> Products -> Software: Alliance Series

7 Tools - Design Manager - Chapter 6 slide 7 Version 1.5 Foundation Software Package contains Design Manager and Foundation Synthesis, Schematic Entry, and Simulation tools –Available on PC for NT and Windows Foundation Software Package Functional Simulation Design Iteration Schematic, Cores HDL Code Simulation Static Timing Analysis, In-Circuit Testing Design Entry Design Verification Design Implementation Design Manager Foundation

8 Tools - Design Manager - Chapter 6 slide 8 Version 1.5 Design Tools Standard CAE entry and verification tools Xilinx software implements the design –The design is optimized for best performance and minimal size –Graphical User Interface and Command Line Interface –Easy access to other Xilinx programs –Manages and tracks design revisions Functional Simulation Back Anno. Schematic, Cores HDL Code Design Implementation Simulation Static Timing Analysis, In-Circuit Testing Design Entry Design Verification Design Manager Foundation or Alliance

9 Tools - Design Manager - Chapter 6 slide 9 Version 1.5 Design Flow for Implementation 1. Invoke Design Manager 2. Start a Project or Open a Project 3. Set up for Implementation 4. Implement the Design 5. Check Timing Results 6. Download the FPGA/CPLD Invoke Foundation Project Manager

10 Tools - Design Manager - Chapter 6 slide 10 Version 1.5 Design Manager Engine Timing Analyzer Static Timing Analysis NGDBUILD Merge Hierarchical Design MAP Logical to Physical translation Groups LUTs and FFs Into CLBs BITGEN Generates configuration file Timing Analyzer Static Timing Estimates PAR Layout of Physical Design Routes Physical Design UCF User Constraint File Configuration Program the FPGA or CPLD XNF or EDIF netlist

11 Tools - Design Manager - Chapter 6 slide 11 Version 1.5 Design Flow Programs What’s under the hood ? Translate (NGDBUILD ) –Merges hierarchical EDIF or XNF files into one file –Contains logical components: combinatorial gates, RAMS, Flip-Flops, etc. MAP –Maps logical components to physical components found in Xilinx FPGA *Look-Up tables, Flip-Flops, Three-State Buffers, etc. –Packs physical components into COMPS (IOBs, CLBs, etc) Timing Analyzer –Use before PAR to analyze timing constraints and estimate design performance –Use after PAR to analyze design performance PAR –Places COMPS on FPGA and routes the FPGA BITGEN –Creates file to configure FPGA

12 Tools - Design Manager - Chapter 6 slide 12 Version 1.5 Outline Design Flow Design Manager Implementation –Design Manager Windows –Design flow to implement the design –Checking results –Configuring, or programming the FPGA Foundation Implementation Summary

13 Tools - Design Manager - Chapter 6 slide 13 Version 1.5 Foundation or Alliance Procedure for both Alliance and Foundation users are given Most steps are similar, except –A few steps are optional for Foundation, and –Tools are invoked differently Alliance on PC and on UNIX –Graphical User Interface (GUI) procedures are same for both –Command line usage can be found with Utilities -> Command History within the Design Manager –Scripts can be used on PC or UNIX

14 Tools - Design Manager - Chapter 6 slide 14 Version 1.5 Step 1: Invoke Design Manager(1) Flow Engine Start and Stop the Flow Engine Timing Analyzer Report on net and path delays Floorplanner Edit design layout PROM File Formatter Configure download data for PROMs Hardware Debugger Download configuration file EPIC Design Editor Device-level view of routing Invoke the Design Manager – Alliance users: select icon, or use command line invocation: dsgnmgr – Foundation users: (optional) select Start -> Programs -> Foundation Series -> Accessories -> Design Manager The Design Manager window appears: Status Window

15 Tools - Design Manager - Chapter 6 slide 15 Version 1.5 Step 1: Invoke Design Manager (cont.) Project Directory containing netlists, also definition of family Version Based on a netlist of the design New version is required when input design is changed Revision An implementation of a Xilinx netlist Multiple revisions typically result from different options or part types Project Versions Revisions Toolbox Menu bar Tool bar

16 Tools - Design Manager - Chapter 6 slide 16 Version 1.5 Step 2: Start a New Project A. Select File -> New Project B. Specify top level input netlist C. Specify working directory D. Use pull-down menu to specify netlist format Alliance users: select the top level netlist in the design – Shown here Foundation users: skip this step

17 Tools - Design Manager - Chapter 6 slide 17 Version 1.5 Step 2: Start a Project (cont.) Set up the design for implementation Select Part Type B. Select Part C. Select Options (...see next foil) A. Select Design -> Implement

18 Tools - Design Manager - Chapter 6 slide 18 Version 1.5 Step 3: Set up for Implementation (1) Use the Constraints Editor to set timing and physical specifications –Define Timing Specification –Lock IO pins Usage: –Alliance users : Select Design Manager -> Tools -> Constraints Editor –Foundation Users: select Start -> Xilinx Foundation Series -> Accessories -> Design Manager -> Tools -> Constraints Editor

19 Tools - Design Manager - Chapter 6 slide 19 Version 1.5 Step 3: Set up for Implementation (2) Enable back annotation file for simulation –Select Design -> Implement -> Options Enable Configuration Data –To generate data to program FPGA/CPLD Enable Timing Analyzer Reports Usage: –Alliance - Select Implement -> Options from Design Manager –Foundation - Select Implementation-> Options from Foundation Project Manager Options Form

20 Tools - Design Manager - Chapter 6 slide 20 Version 1.5 Step 4: Implement the Design Implementation Places and Routes your design, and creates a file to program the FPGA or CPLD Usage –Alliance Users - select Design -> Implement -> Run from the Design Manager –Foundation Users - select Implementation -> Run from the Foundation Project Manager

21 Tools - Design Manager - Chapter 6 slide 21 Version 1.5 Step 4: Implement the Design (cont.) l Once implementation is started, the “Run-only” Flow Engine appears – Tracks status of your design, and allows you to stop or pause

22 Tools - Design Manager - Chapter 6 slide 22 Version 1.5 Step 5A. Check Results Reports are generated throughout the Design Flow Reports will be discussed in the next chapter and in lab From Design Manager, select Report Browser

23 Tools - Design Manager - Chapter 6 slide 23 Version 1.5 Step 5B. Analyze Static Timing Displays delays for any path or timing constraint in your design Provides detailed breakdown of each delay path, including – net delay – component delay – primitive delay Usage : – Alliance users: select Design Manager -> Timing Analyzer – Foundation users: select Start -> Foundation Series -> Accessories -> Design Manager -> Timing Analyzer

24 Tools - Design Manager - Chapter 6 slide 24 Version 1.5 Step 6: Configure the FPGA/CPLD To configure, or program FPGAs, a bit file is created and downloaded –Configuration can be driven by a microprocessor –Data can be stored in a PROM –Enable Produce Configuration Data (Flow Engine -> Setup -> Options) before implementation To configure CPLDs, a JTAG file is downloaded –CPLDs can be configured In-System, or –CPLDs can be configured using third party programmers Alliance : Design ->Implement -> Options Foundation : Implementation -> Options

25 Tools - Design Manager - Chapter 6 slide 25 Version 1.5 Step 6: Configuration Methods

26 Tools - Design Manager - Chapter 6 slide 26 Version 1.5 Outline Design Flow Design Manager Implementation –Design Manager Windows –Design flow to implement the design –Checking results –Configuring, or programming the FPGA Foundation Implementation Summary

27 Tools - Design Manager - Chapter 6 slide 27 Version 1.5 Simple Foundation Implementation Foundation is both simple to use and powerful –To implement your design, simply select simply select Implementation -> Run from the Foundation Project Manager Window For simple implementation, all tools are located in Foundation Project Manager –Invoke with Start -> Programs -> Xilinx Foundation Series -> Xilinx Foundation Project Manager For customized implementation, tools are located at Start -> Programs -> Xilinx Foundation Series -> Accessories -> Design Manager

28 Tools - Design Manager - Chapter 6 slide 28 Version 1.5 Foundation Methodology Chart More information is available in the On-Line documents. Also,Xilinx offers one-day Foundation class and Foundation Express classes

29 Tools - Design Manager - Chapter 6 slide 29 Version 1.5 Outline Design Flow Steps to Implement the design with Design Manager –Design Manager Windows –Design flow to implement the design –Checking results –Configuring, or programming the FPGA Design Manager Implementation Summary

30 Tools - Design Manager - Chapter 6 slide 30 Version 1.5 Summary Design Manager is a fast, simple tool to implement an FPGA design The techniques just covered were for a simple design Powerful options for larger and faster designs are discussed in the high density design materials Summary for Foundation follows

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