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Generators 1 Object Oriented Generators in Java Michael Chu & Nicholas Weaver.

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Presentation on theme: "Generators 1 Object Oriented Generators in Java Michael Chu & Nicholas Weaver."— Presentation transcript:

1 Generators 1 Object Oriented Generators in Java Michael Chu & Nicholas Weaver

2 Generators 2 Roadmap OO generators Automatic services Component libraries Future goals

3 Generators 3 Why Java? 100% Pure Buzzword Compliant

4 Generators 4 Why Java? Reasonably nice Politically acceptable Object Oriented Good metadata interface

5 Generators 5 What are OO Generators? A component: –Contains subcomponents which represent the pieces of a design –Has a constructor which creates the subcomponents and attaches them together –Has connections for interfacing with other components –Any additional routines for additional functionality

6 Generators 6 What are OO Generators? Adder Multiplier Register I0 I1 O MAC I0 I1 O Add I0 I1 O Multiply D Q Register

7 Generators 7 Why Object Oriented? Allows smart components –Partial evaluation and simulation –Components can change once created Different instances of the same class can behave differently Convenient abstractions for automatic services –Can treat the design as a hierarchical tree or a graph of components

8 Generators 8 A Hierarchical Tree Each component is made up of subcomponents Tree structure captures the design hierarchy and programmer intuition Routine provides access to all child components and the parent component Used for automatic placement and evaluation ordering

9 Generators 9 A Hierarchical Tree Adder Multiplier Register I0 I1 O MAC I0 I1 O Add I0 I1 O Multiply D Q Register

10 Generators 10 A Graph of Components Each component has a set of inputs and outputs Can follow all inputs and outputs, backwards and forwards

11 Generators 11 A Graph of Components Adder Multiplier Register I0 I1 O MAC I0 I1 O Add I0 I1 O Multiply D Q Register

12 Generators 12 Examining objects java.lang.reflect package allows inspection of objects Can access all slots and methods and determine type Used to allow iteration over all subcomponents, inputs, and outputs Automated creation of backpointers

13 Generators 13 Automatic Services Logic Trimming –Traces the graph from the array inputs and outputs Partial Evaluation –Constant propagation –Structural changes based on inputs Simulation Netlist generation

14 Generators 14 Partial Evaluation Library components can examine their inputs, and if possible, assign outputs or rearrange internal structure Changes are then propagated to dependant components in an iterative process –Connection values are never changed, only set, guaranteeing convergence

15 Generators 15 Partial Evaluation Example Adder Multiplier Register I0 I1 O MAC I0 I1 O Add I0 I1 O Multiply D Q Register 0

16 Generators 16 Partial Evaluation Example Adder Multiplier Register I0 I1 O I0 I1 O Add D Q Register 0 0

17 Generators 17 Partial Evaluation Example Adder Multiplier Register I0 I1 O D Q Register 0

18 Generators 18 Simulation Library leaf nodes implement simulation routines. Changes are propagated similar to the partial evaluation system Assumes synchronous design

19 Generators 19 Simulation for testing Larger components can implement a behavioral simulation routine Both routines automatically run concurrently –Differences produce warning messages

20 Generators 20 Component Libraries Use the framework to build a series of libraries –Platform independent API –Include specialization and simulation routines –Perform netlist generation and similar services

21 Generators 21 Target Platforms Targets: –Xilinx 4000E –Garp –Hierarchical Array All targets should have identical high-level primitives available –But implementations may use different details Low-level primitives can be target specific

22 Generators 22 Current Status Basic structure completed Some automatic services –Logic trimming, simulation, partial evaluation Basic components of XC4000 library Simple designs completed –Counters, DNA sequence matching

23 Generators 23 Future Development Simple control logic synthesis More components for Xilinx library Automatic and semi-automatic placement routines More supported platforms Real designs –Compare designs with those produced by HDL and schematic capture


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