1. An Integrated Design Environment to Evaluate Power/Performance Tradeoffs for Sensor Network Applications Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna Dept. of Electrical Engineering - Systems University of Southern California Los Angeles, CA funded by the DARPA Power-aware Computing and Communications program Project URL: http://milan.usc.edu/

2. HPEC 2002 Prasanna: 2 MILAN: A Model-based Integrated Simulation Framework A unified environment capable of: –modeling a large class of embedded systems and applications –driving design space exploration tools for rapid evaluation of a large design space –seamlessly integrating different widely-used simulators into a single framework for hierarchical simulation –enabling rapid evaluation of different performance metrics such as energy, latency, and throughput Use coarse system models based on key parameters Reduce initial design choices Use low-level simulators to analyze the reduced design options Choose one (or more) designs for implementation Initial design space ~10 5 -10 6 Design space pruning Hierarchical simulation ~100 ~10

3. HPEC 2002 Prasanna: 3 Design Flow in MILAN Application (Task Graph) Hardware Resources Generic Modeling Environment (GME 2000) Application Model Resource Model Constraints Offline Estimates Design Space Design Space Exploration (analytical technique) Instruction Level Simulator Cycle Accurate Simulator RT-level Simulator Final Design Identify a set of designs Hierarchical Simulation Level of abstraction Accuracy High-level Perf. Estimator

4. HPEC 2002 Prasanna: 4 I. Energy-Efficient Design of Sensor Network Applications MEMORY Sensors RADIO BUS (D VS ) PROCESSOR fd SENSOR fd SENSOR fd SENSOR fd SENSOR fd SENSOR fd SENSOR fd SENSOR A modeling and simulation environment for power-aware design of a multi-node sensor network Multi-granularity simulation Simulator integration –Results from Wattch simulation are used to automatically configure ns-2 parameters –Results from Wattch/ns-2 are used to automatically refine parameters for high-level estimator

5. HPEC 2002 Prasanna: 5 II. Energy-Efficient Design of Kernel Applications for FPGAs EAT (million nJ  slices  cycles) Matrix Size XilinxUni- proc. Linear Array 3  3 0.20.1 6  6 41.23.93.5 9  9 469.539.232.5 15  15 10063.3839.77580.0 Domain selection Domain- specific modeling Low-level simulation of candidate designs Tradeoff analysis and design space exploration Kernel applicatio n Energy - efficient design Low-level simulators (XPower, ModelSim,…) VHDL code MILAN Architecture, parameters (ranges) Power estimates Power function builder (curve fitting …) Model interpreters Component specific power function