1. Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 16, 2011 Memory Periphery

2. Today Decode Sensing Penn ESE370 Fall2011 -- DeHon 2

3. Memory Bank Penn ESE370 Fall2011 -- DeHon 3

4. Row Select Logically a big AND –May include an enable for timing in synchronous Penn ESE370 Fall2011 -- DeHon 4 How many transistors (per bit)?

5. How tall is a row? Side length for cell of size: –1000 2 – 600 2 – 100 2 Penn ESE370 Fall2011 -- DeHon 5

6. 6 How tall is an AND? Penn ESE370 Fall 2011 -- Townley & DeHon 2 6 6 3 2 2

7. Row Select How can we do better? –Area –Delay –Match to pitch of memory row Penn ESE370 Fall2011 -- DeHon 7

8. Row Select Compute inversions outside array –Just AND appropriate line (bit or /bit) Penn ESE370 Fall2011 -- DeHon 8

9. Row Select Share common terms Multi-level decode Penn ESE370 Fall2011 -- DeHon 9

10. Row Select Same number of lines Half as many AND inputs Penn ESE370 Fall2011 -- DeHon 10

11. Row Select: Precharge NAND Penn ESE370 Fall2011 -- DeHon 11

12. Row Select: Precharge NOR Penn ESE370 Fall2011 -- DeHon 12

13. Sensing Penn ESE370 Fall2011 -- DeHon 13

14. Penn ESE370 Fall2011 -- DeHon 14 SRAM Memory bit

15. Simulation W access =20 Penn ESE370 Fall2011 -- DeHon 15

16. Sense Small Swings What do we have to worry about? Penn ESE370 Fall2011 -- DeHon 16

17. Sense Small Swings Variation Common mode noise Penn ESE370 Fall2011 -- DeHon 17

18. Differential Sense Amp Goal: –Reject common shift Penn ESE370 Fall2011 -- DeHon 18

19. Differential Sense Amp Penn ESE370 Fall2011 -- DeHon 19

20. What doe this do? Output when: –In=Gnd? –In=Vdd? –Transfer curve? Penn ESE370 Fall2011 -- DeHon 20

21. “Inverter” Input high –Ratioed like grounded P Input low –Pulls itself up –Until V dd -V TP Penn ESE370 Fall2011 -- DeHon 21

22. DC Transfer Function Penn ESE370 Fall2011 -- DeHon 22

23. Differential Sense Amp Penn ESE370 Fall2011 -- DeHon 23

24. Diffamp Transfer Function in=/in, looks like “inverter” Deliberately low gain in mid region Penn ESE370 Fall2011 -- DeHon 24

25. Differential Sense Amp “Inverter” output controls PMOS for second inverter Sets PMOS operating point –current Penn ESE370 Fall2011 -- DeHon 25

26. Differential Sense Amp View: –Current mirror –Biases where inverter operating Penn ESE370 Fall2011 -- DeHon 26

27. Differential Sense Amp View: – adjusting the pullup load resistance –Changing the trip point for “inverter” Penn ESE370 Fall2011 -- DeHon 27

28. DC Transfer /in with in=0.5V Penn ESE370 Fall2011 -- DeHon 28

29. DC Transfer Various in Penn ESE370 Fall2011 -- DeHon 29

30. After Inverter Penn ESE370 Fall2011 -- DeHon 30

31. Ramp 50mV Offset Penn ESE370 Fall2011 -- DeHon 31

32. Closeup 50mV Offset Penn ESE370 Fall2011 -- DeHon 32

33. Connect to Column Equalize lines during precharge Penn ESE370 Fall2011 -- DeHon 33

34. Singled-Ended Read Penn ESE370 Fall2011 -- DeHon 34

35. 5T SRAM Penn ESE370 Fall2011 -- DeHon 35

36. Single Ended Given same problems –How sense small swing on single-ended case? Penn ESE370 Fall2011 -- DeHon 36

37. Single Ended Need reference to compare against Want to look just like bit line Equalize with bit line Penn ESE370 Fall2011 -- DeHon 37

38. Split Bit Line Split bit-line in half Precharge/equalize both Word in only one half –Only it switches Amplify difference Penn ESE370 Fall2011 -- DeHon 38

39. Open Bit Line Architecture For 1T DRAM Add dummy cells Charge dummy cells to V dd /2 “read” dummy in reference half Penn ESE370 Fall2011 -- DeHon 39

40. Memory Bank Penn ESE370 Fall2011 -- DeHon 40

41. Energy Penn ESE370 Fall2011 -- DeHon 41

42. Single Port Memory What fraction is involved in a read/write? What are most cells doing on a cycle? Reads are slow –Cycles long  lots of time to leak Penn ESE370 Fall2011 -- DeHon 42

43. ITRS 2009 45nm Penn ESE370 Fall2011 -- DeHon 43 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV C 0 = 0.045  m × C g,total

44. High Power Process V=1V d=1000  =0.5 W access =W buf =2 Full swing for simplicity C sc = 0 –(just for simplicity, typically <C load ) BL: C load =1000C 0 ≈ 45 fF = 45×10 -15 F W N = 2  I leak = 9×10 -9 A P= (45×10 -15 ) freq + 1000×9×10 -9 W Penn ESE370 Fall2011 -- DeHon 44

45. Relative Power P= (45×10 -15 ) freq + 1000×9×10 -9 W P= (4.5×10 -14 ) freq + 9×10 -6 W Crossover freq<200MHz How partial swing on bit line change?  Reduce dynamic energy  Increase percentage in leakage energy  Reduce crossover frequency Penn ESE370 Fall2011 -- DeHon 45

46. Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process or transistors with high V th –Reduce leakage at expense of speed Penn ESE370 Fall2011 -- DeHon 46

47. Admin Project –Should Have memory cell –Add drivers and amps Penn ESE370 Fall2011 -- DeHon 47

48. Idea Minimize area of repeated cell Compensate with periphery –Amplification (restoration) Match periphery pitch to cell row/column –Decode –Sensing –Writer Drivers Penn ESE370 Fall2011 -- DeHon 48