1. Introduction to High Momentum Trigger in PHENIX Muon Arms RIKEN/RBRC Itaru Nakagawa 中川格 1

2. 2 RHIC Accelerator Complex 2 2003200420052006200720082009201020112012 200G eV 500G eV testproduction testproduction

3. Forward (North&South) Muon Arms

4. 4 Muon Tracker Stations and Octants

5. 5 5 1.Muon Tracking Chambers – 3 stations of Cathode strip chambers – Each station has multiple planes for redundancy – Slow read out -> No trigger 2.Muon Identifier – 5 layers of Iarocci tubes in x and y – 80 cm of steel plate absorber (total) – Provides trigger p  > 2 GeV St#1 St#2 St#3 MuTr Same configuration in South MuID   B Current Muon System

6. 6 Trigger Rate @ sqrt(s) = 200 GeV 100 GeV  -Trigger Rate < 2 kHz

7. 7 Trigger Rate @ sqrt(s) = 500 GeV 250 GeV Rate ~ 9 MHz !! Design Luminosity √s = 500 GeV σ=60mb L = 1.5x10 32 /cm 2 /s Rejection Factor ~ 4500 

8. 8 High Momentum Muon Trigger Run11 500 GeV Projection New Trigger Upgrade MuID Trigger Rate 9 MHz 90 kHz σ tot =60mb L=1.5x10 32 cm -2 s -1 BBC  MuID Rejection Power RP~100 Trigger Upgrade RP ~ 45 2 kHz PHENIX Band Width for Muon Required Rejection Power RP tot ~ 4500 1.High Rejection Power 2.High Efficiency 1.High Rejection Power 2.High Efficiency W

9. 9 R1(a+b) R3 r=3.40m MuTr (I)Three dedicated trigger RPC stations (CMS design): R1(a,b): ~12mm in , 4x θ pads R2: ~5.4mm in , 4x θ pads R3: ~6.0mm in , 4x θ pads (Trigger only – offline segmentation higher) NSF (Funded) JSPS (Funded) (II)MuTr front end electronics Upgrade to allow LL1 information Rejection ~12,000, beam background immune. PHENIX Muon Trigger Upgrade

10. 10 Momentum Dependent Trigger B 10 How New Trigger Works? Search for a Stiff Track ONLINE! Slow MuTr could trigger with INCOMING tracks Fast RPC will reject them P T Sensitive Trigger Does The Job

11. 11 W Trigger System MuTr FEE B Trigger Interaction Region Rack Room Trigger events with straight track (e.g.  strip <= 1) ~10  s

12. 12 W Trigger System MuTRG ADTX MuTRG MRG MuTr FEE B 2 planes 5% 95% Trigger Interaction Region Rack Room Optical 1.2Gbps Amp/Discri. Transmit Data Merge MuTRG Trigger events with straight track (e.g.  strip <= 1)

13. 13 W Trigger System MuTRG ADTX MuTRG MRG MuTr FEE Resistive Plate Counter (RPC) (Φ segmented) B 2 planes 5% 95% Trigger Interaction Region Rack Room Optical 1.2Gbps Amp/Discri. Transmit Data Merge MuTRG RPC FEE RPC / MuTRG data are also recorded on disk. Trigger events with straight track (e.g.  strip <= 1)

14. 14 W Trigger System MuTRG ADTX MuTRG MRG Level 1 Trigger Board MuTr FEE Resistive Plate Counter (RPC) (Φ segmented) B 2 planes 5% 95% Trigger Interaction Region Rack Room Optical 1.2Gbps Amp/Discri. Transmit Data Merge MuTRG RPC FEE Trigger events with straight track (e.g.  strip <= 1) RPC / MuTRG data are also recorded on disk.

15. 15 W Trigger System MuTRG ADTX MuTRG MRG Level 1 Trigger Board MuTr FEE Resistive Plate Counter (RPC) (Φ segmented) B 2 planes 5% 95% Trigger Interaction Region Rack Room Optical 1.2Gbps Amp/Discri. Transmit Data Merge MuTRG RPC FEE Trigger events with straight track (e.g.  strip <= 1) RPC / MuTRG data are also recorded on disk.

16. 16 W Trigger System (Final) MuTRG ADTX MuTRG MRG Level 1 Trigger Board MuTr FEE Resistive Plate Counter (RPC) (Φ segmented) B 2 planes 5% 95% Trigger Interaction Region Rack Room Optical 1.2Gbps Amp/Discri. Transmit Data Merge MuTRG RPC FEE Trigger events with straight track (e.g.  strip <= 1) RPC / MuTRG data are also recorded on disk. DCM

17. 17 MuTrig-FEE Developers MuTRG ADTX MuTRG MRG ADTX Board Yoshi Fukao Kohei Shoji Kazuya Aoki Katsuro Nakamura Kenichi Karatsu Tsutomu Mibe MRG Board & DCMIF

18. Installation 18 2008 North Arm 2009 South Arm

19. 19 New MuTRIG-FEE in North Arm  Before Install 2008 Install 

20. MuTrig-FEE Parameters FunctionOptions DiscriminatorLEDCFD Threshold0 ~ 100 mV (40,60mV) Gap LOGICOR AND 2 of 33 of 3 LL1 Width1 ~ 7 (2,3) St1 St2 St3 2 of 3 AND 3 of 3 AND No MuTRG-FEE MuTR Non-Stereo Gaps MuTR Non-Stereo Gaps 20

21. Resistive Plate Chamber (RPC) 21

22. 22

23. 23

24. 24 Hadron Absorber

25. 25

26. 26 Neutron Absorber + RPC1 Yoshimitsu ImazuKentaro Watanabe How much neutron backgrounds? How we can reduce these background effect? How much neutron backgrounds? How we can reduce these background effect? Recap clamp

27. MuTR-FEE Trigger Performance 27

28. MuTRG System Run09 performance 28 MuID Algorithm Track Matching w/ MuID Timing cut w/ RPC Track Matching w/ RPC Neutron Backgrounds etc.. MuID Algorithm Track Matching w/ MuID Timing cut w/ RPC Track Matching w/ RPC Neutron Backgrounds etc..  MuTrg-FEE x MuID Better efficiency is the trade off of weak rejection power

29. LL1 Efficiencies ADTX MuTr MRG LL1 DCMIF DCM GL1 Trigger Identical hit information Identical hit information Josh Perry’s Online Monitor LL1 boards developed by U.Iowa

30. LL1 Trigger Emulator Online Plot LL1 efficiency Stability Monitored by Sanghwa Park (SNU)

31. Summary Forward Muon Trigger Upgrade hardware developments are nearly final stage. Thanks for many students / young researchers. We continue to improve performance of existing detectors (hardware and software wise). Physics Analysis (not only W), performance improvement, trigger operation, maintenance, etc… There are many things to do! 31

32. Back up Slides 32

33. Efficiency Turn on Curve 33 New Trigger Upgrade MuID Trigger W black : offline emulator red : GL1 fired Not firing by low momentum track!

34. MuTR-FEE SG1 Trigger Before Long Shutdown After Long Shutdown PHENIX Band Width Limit for Muon Rejection Power Improved Rejection Power after Long Shutdown or OR->AND2 Logic? OR AND2 34 Surviving BBC rate 2MHz!

35. Summary New Muon Trigger-FEE SG1 trigger is under operation as physics trigger for W LL1 demonstrates stable performance w/ almost 100% efficiencies for both North&South Trigger efficiency behaves pretty much as we designed. Low efficiency in low P T, high efficiency in high P T regions. SG1xMUIDxBBC trigger functions with sufficient rejection power so far up to BBC rate ~ 2MHz. Combined with RPC will provide even stronger and more reliable trigger for W. 35