1. Spring 2010, Mar 10ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Gate Sizing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10

2. Clock Distribution clock Spring 2010, Mar 102ELEC 7770: Advanced VLSI Design (Agrawal)

3. Clock Power P clk = C L V DD 2 f + C L V DD 2 f / λ + C L V DD 2 f / λ 2 +... stages – 1 1 = C L V DD 2 f Σ─ n= 0 λ n where C L =total load capacitance λ =constant fanout at each stage in distribution network Clock consumes about 40% of total processor power. Spring 2010, Mar 103ELEC 7770: Advanced VLSI Design (Agrawal)

4. Delay of a CMOS Gate CMOS gate CLCL CgCg C int Propagation delay through the gate: t p = 0.69 R eq (C int + C L ) ≈ 0.69 R eq C g (1 + C L /C g ) = t p0 (1 + C L /C g ) Gate capacitance Intrinsic capacitance Spring 2010, Mar 104ELEC 7770: Advanced VLSI Design (Agrawal)

5. R eq, C g, C int, and Width Sizing  R eq : equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = sizing factor  C g : gate capacitance, proportional to C ox WL; scales as S  C int : intrinsic output capacitance ≈ C g, for submicron processes  t p0 : intrinsic delay = 0.69R eq C g ; independent of sizing Spring 2010, Mar 105ELEC 7770: Advanced VLSI Design (Agrawal)

6. Effective Fan-out, f  Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: f=C L /C g t p =t p0 (1 + f ) Spring 2010, Mar 106ELEC 7770: Advanced VLSI Design (Agrawal)

7. Sizing an Inverter Chain Cg1Cg1 Cg2Cg2 CLCL 12N C g2 = f2C g1 t p1 = t p0 (1 + C g2 /C g1 ) t p2 = t p0 (1 + C g3 /C g2 )N t p =Σ t pj =t p0 Σ (1 + C gj+1 /C gj ) j=1j=1 Spring 2010, Mar 107ELEC 7770: Advanced VLSI Design (Agrawal)

8. Minimum Delay Sizing Equate partial derivatives of t p with respect to C gj to 0: 1/C g1 – C g3 /C g2 2 = 0, etc. or C g2 2 = C g1 ×C g3, etc. i.e., gate capacitance is geometric mean of forward and backward gate capacitances. Also, C g2 /C g1 = C g3 /C g2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: C L /C g1 = F = f N, t p = Nt p0 (1 + F 1/N ) Spring 2010, Mar 108ELEC 7770: Advanced VLSI Design (Agrawal)

9. Minimum Delay Sizing Equate partial derivatives of t p with respect to N to 0: dNt p0 (1 + F 1/N ) ───────── = 0 dN i.e., F 1/N – F 1/N (ln F)/N = 0 or ln f = 1 → f = e = 2.7 and N = ln F Spring 2010, Mar 109ELEC 7770: Advanced VLSI Design (Agrawal)

10. Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Section 5.4. Spring 2010, Mar 1010ELEC 7770: Advanced VLSI Design (Agrawal)

11. Summary  Device sizing combined with supply voltage reduction reduces energy consumption.  For large fan-out energy reduction by a factor of 10 is possible.  An exception is F = 1 case, where the minimum size device is also the most effective one.  Oversizing the devices increases energy consumption. Spring 2010, Mar 1011ELEC 7770: Advanced VLSI Design (Agrawal)