1. George Mason University ECE 545 – Introduction to VHDL Data types Timing in VHDL ECE 545 Lecture 13

2. 2ECE 545 – Introduction to VHDL Sources & Required Reading Peter Ashenden, The Designer’s Guide to VHDL, Chapter 2 Scalar Data Types and Operations Chapter 4 Composite Data Types and Operations

3. 3ECE 545 – Introduction to VHDL VHDL as a Strongly Typed Language

4. 4ECE 545 – Introduction to VHDL Notion of type Type defines a set of values and a set of applicable operations Declaration of a type determines which values can be stored in an object (signal, variable, constant) of a given type Every object can only assume values of its nominated type Each operation (e.g., and, +, *) includes the types of values to which the operation may be applied, and the type of the result The goal of strong typing is a detection of errors at an early stage of the design process

5. 5ECE 545 – Introduction to VHDL Example of strong typing architecture incorrect of example1 is type apples is range 0 to 100; type oranges is range 0 to 100; signal apple1: apples; signal orange1: oranges; begin apple1 <= orange1; end incorrect;

6. 6ECE 545 – Introduction to VHDL Type Classification

7. 7ECE 545 – Introduction to VHDL Classification of data types

8. 8ECE 545 – Introduction to VHDL Integer Types

9. 9ECE 545 – Introduction to VHDL Integer type Name: integer Status: predefined Contents:all integer numbers representable on a particular host computer, but at least numbers in the range –(2 31 -1).. 2 31 -1

10. 10ECE 545 – Introduction to VHDL User defined integer types - Examples type day_of_month is range 0 to 31; type year is range 0 to 2100; type set_index_range is range 999 downto 100; constant number_of_bits: integer :=32; type bit_index is range 0 to number_of_bits-1; Values of bounds can be expressions, but need to be known when the model is analyzed.

11. 11ECE 545 – Introduction to VHDL Enumeration Types

12. 12ECE 545 – Introduction to VHDL Predefined enumeration types (1) boolean(true, false) bit(‘0’, ‘1’) characterVHDL-87: 128 7-bit ASCII characters VHDL-93: 256 ISO 8859 Latin-1 8-bit characters

13. 13ECE 545 – Introduction to VHDL Predefined enumeration types (2) severity_level (note, warning, error, failure) Predefined in VHDL-93 only: file_open_kind (read_mode, write_mode, append_mode) file_open_status (open_ok, status_error, name_error, mode_error)

14. 14ECE 545 – Introduction to VHDL User-defined enumeration types - Examples type state is (S0, S1); type alu_function is (disable, pass, add, subtract, multiply, divide); type octal_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’); type mixed is (lf, cr, ht, ‘-’, ‘/‘, ‘\’); Each value in an enumeration type must be either an identifier or a character literal

15. 15ECE 545 – Introduction to VHDL Floating-Point Types

16. 16ECE 545 – Introduction to VHDL Floating point types Used to represent real numbers Numbers are represented using a significand (mantissa) part and an exponent part Conform to the IEEE standard 754 or 854 Minimum size of representation that must be supported by the implementation of the VHDL standard: VHDL-2001: 64-bit representation VHDL-87, VHDL-93: 32-bit representation

17. 17ECE 545 – Introduction to VHDL Real literals - examples23.1 46E546  10 5 1E+121  10 12 1.234E091.234  10 9 34.0e-0834.0  10 -8 2#0.101#E50.101 2  2 5 =(2 -1 +2 -3 )  2 5 8#0.4#E-60.4 8  8 -6 = (4  8 -1 )  8 -6 16#0.a5#E-80.a5 16  16 -8 =(10  16 -1 +5  16 -2 )  16 -8

18. 18ECE 545 – Introduction to VHDL The ANSI/IEEE standard floating-point number representation formats

19. 19ECE 545 – Introduction to VHDL User-defined floating-point types - Examples type input_level is range -10.0 to +10.0 type probability is range 0.0 to 1.0; constant max_output: real := 1.0E6; constant min_output: real := 1.0E-6; type output_range is max_output downto min_output;

20. 20ECE 545 – Introduction to VHDL Attributes of Scalar Types

21. 21ECE 545 – Introduction to VHDL Attributes of all scalar types T’leftfirst (leftmost) value in T T’rightlast (rightmost) value in T T’lowleast value in T T’highgreatest value in T Not available in VHDL-87: T’ascending true if T is an ascending range, false otherwise T’image(x)a string representing the value of x T’value(s)the value in T that is represented by s

22. 22ECE 545 – Introduction to VHDL type index_range is range 21 downto 11; index_range’left = 21 index_range’right = 11 index_range’low = 11 index_range’high = 21 index_range’ascending = false index_range’image(14)= “14” index_range’value(“20”)= 20 Attributes of all scalar types - examples

23. 23ECE 545 – Introduction to VHDL Attributes of discrete types T’pos(x)position number of x in T T’val(n)value in T at position n T’succ(x)value in T at position one greater than position of x T’pred(x)value in T at position one less than position of x T’leftof(x)value in T at position one to the left of x T’rightof(x) value in T at position one to the right of x

24. 24ECE 545 – Introduction to VHDL type logic_level is (unknown, low, undriven, high); logic_level’pos(unknown)= 0 logic_level’val(3) = high logic_level’succ(unknown) = low logic_level’pred(undriven) = low logic_level’leftof(unknown) error logic_level’rightof(undriven)= high Attributes of discrete types - examples

25. 25ECE 545 – Introduction to VHDL Subtypes

26. 26ECE 545 – Introduction to VHDL Subtype Defines a subset of a base type values A condition that is used to determine which values are included in the subtype is called a constraint All operations that are applicable to the base type also apply to any of its subtypes Base type and subtype can be mixed in the operations, but the result must belong to the subtype, otherwise an error is generated.

27. 27ECE 545 – Introduction to VHDL Predefined subtypes naturalintegers  0 positiveintegers > 0 Not predefined in VHDL-87: delay_lengthtime  0

28. 28ECE 545 – Introduction to VHDL User-defined subtypes - Examples subtype bit_index is integer range 31 downto 0; subtype input_range is real range 1.0E-9 to 1.0E+12;

29. 29ECE 545 – Introduction to VHDL Operators

30. 30ECE 545 – Introduction to VHDL Operators (1)

31. 31ECE 545 – Introduction to VHDL Operators (2)

32. 32ECE 545 – Introduction to VHDL Operators (3)

33. 33ECE 545 – Introduction to VHDL Operator Overloading

34. 34ECE 545 – Introduction to VHDL Operator overloading Operator overloading allows different argument types for a given operation (function) The VHDL tools resolve which of these function to select based on the types of the inputs This selection is transparent to the user as long as the function has been defined for the given argument types.

35. 35ECE 545 – Introduction to VHDL Different declarations for the same operator - Example Declarations in the package ieee.std_logic_unsigned: function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function “+” ( L: std_logic_vector; R: integer) return std_logic_vector; function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector;

36. 36ECE 545 – Introduction to VHDL Different declarations for the same operator - Example signal count: std_logic_vector(7 downto 0); You can use: count <= count + “0000_0001”; or count <= count + 1; or count <= count + ‘1’;

37. 37ECE 545 – Introduction to VHDL Specifying time in VHDL

38. 38ECE 545 – Introduction to VHDL Physical data types Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types. TIME is the only predefined physical data type. Value of the physical data type is called a physical literal.

39. 39ECE 545 – Introduction to VHDL Time values (physical literals) - Examples 7 ns 1 min min 10.65 us 10.65 fs Unit of time (dimension) SpaceNumeric value

40. 40ECE 545 – Introduction to VHDL TIME values Numeric value can be an integer or a floating point number. Numeric value is optional. If not given, 1 is implied. Numeric value and dimension MUST be separated by a space.

41. 41ECE 545 – Introduction to VHDL Units of time UnitDefinition Base Unit fsfemtoseconds (10 -15 seconds) Derived Units pspicoseconds (10 -12 seconds) nsnanoseconds (10 -9 seconds) usmicroseconds (10 -6 seconds) msmiliseconds (10 -3 seconds) secseconds minminutes (60 seconds) hrhours (3600 seconds)

42. 42ECE 545 – Introduction to VHDL Values of the type TIME Value of a physical literal is defined in terms of integral multiples of the base unit, e.g. 10.65 us = 10,650,000,000 fs 10.65 fs = 10 fs Smallest available resolution in VHDL is 1 fs. Smallest available resolution in simulation can be set using a simulator command or parameter.

43. 43ECE 545 – Introduction to VHDL Arithmetic operations on values of the type TIME Examples: 7 ns + 10 ns = 17 ns 1.2 ns – 12.6 ps = 1187400 fs 5 ns * 4.3 = 21.5 ns 20 ns / 5ns = 4

44. 44ECE 545 – Introduction to VHDL Propagation delay in VHDL

45. 45ECE 545 – Introduction to VHDL Propagation delay in VHDL - Example entity MAJORITY is port (A_IN, B_IN, C_IN : in STD_LOGIC; Z_OUT : out STD_LOGIC); end MAJORITY; architecture DATA_FLOW of MAJORITY is begin Z_OUT <= (not A_IN and B_IN and C_IN) or (A_IN and not B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 20 ns; end DATA_FLOW;

46. 46ECE 545 – Introduction to VHDL Propagation delay - Example

47. 47ECE 545 – Introduction to VHDL MLU: Block Diagram

48. 48ECE 545 – Introduction to VHDL MLU - Architecture Body – Example 1 begin A1<= not A after 6 ns when (NEG_A='1') else A after 5 ns; B1<= not B after 6 ns when (NEG_B='1') else B after 5 ns; Y <= not Y1 after 6 ns when (NEG_Y='1') else Y1 after 5 ns; MUX_0 <= A1 and B1 after 3 ns; MUX_1 <= A1 or B1 after 3 ns; MUX_2 <= A1 xor B1 after 4 ns; MUX_3 <= A1 xnor B1 after 5 ns; L<=L1 & L0; with (L) select Y1 <= MUX_0 after 7 ns when "00", MUX_1 after 6 ns when "01", MUX_2 after 8 ns when "10", MUX_3 after 7 ns when others; end MLU_DATAFLOW;

49. 49ECE 545 – Introduction to VHDL MLU - Architecture Body – Example 2 begin A1<= not A after MUX2_delay when (NEG_A='1') else A after MUX_2_delay; B1<= not B after MUX2_delay when (NEG_B='1') else B after MUX2_delay; Y <= not Y1 after MUX2_delay when (NEG_Y='1') else Y1 after MUX2_delay; MUX_0 <= A1 and B1 after GATE_delay; MUX_1 <= A1 or B1 after GATE_delay; MUX_2 <= A1 xor B1 after XOR_delay; MUX_3 <= A1 xnor B1 after XOR_delay; L<=L1 & L0; with (L) select Y1 <= MUX_0 after MUX4_delay when "00", MUX_1 after MUX4_delay when "01", MUX_2 after MUX4_delay when "10", MUX_3 after MUX4_delay when others; end MLU_DATAFLOW;

50. 50ECE 545 – Introduction to VHDL Delay constants constant MUX2_delay: time := 5 ns; constant GATE_delay: time := 3 ns; constant XOR_delay: time := 4 ns; constant MUX4_delay: time := 7 ns; Can be defined in the declarative portion of the architecture or in the package

51. 51ECE 545 – Introduction to VHDL Inertial delay model

52. 52ECE 545 – Introduction to VHDL Inertial delay model Short pulses (spikes) are not passed to the outputs of logic gates due to the inertia of physical systems. Logic gates behave like low pass filters and effectively filter out high frequency input changes as if they never occurred.

53. 53ECE 545 – Introduction to VHDL Inertial delay model - Example SIG_OUT <= not SIG_IN after 7 ns

54. 54ECE 545 – Introduction to VHDL VHDL-87 Inertial delay model Any input signal change that does not persist for at least a propagation delay of the device is not reflected at the output. inertial delay (pulse rejection limit) = propagation delay

55. 55ECE 545 – Introduction to VHDL VHDL-93 Enhanced inertial delay model VHDL-93 allows the inertial delay model to be declared explicitly as well as implicitly. Explicitly: Z_OUT <= inertial (not A_IN and B_IN and C_IN) or (A_IN and not B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 20 ns; Implicitly: Z_OUT <= (not A_IN and B_IN and C_IN) or (A_IN and not B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 20 ns;

56. 56ECE 545 – Introduction to VHDL VHDL-93 Enhanced inertial delay model VHDL-93 allows inertial delay, also called a pulse rejection limit, to be different from the propagation delay. SIG_OUT <= reject 5 ns inertial not SIG_IN after 7 ns;

57. 57ECE 545 – Introduction to VHDL Transport delay model With a transport delay model, all input signal changes are reflected at the output, regardless of how long the signal changes persist. Transport delay model must be declared explicitly using the keyword transport. Inertial delay model is a default delay model because it reflects better the actual behavior of logic components. Transport delay model is used for high-level modeling.

58. 58ECE 545 – Introduction to VHDL Transport delay model - Example SIG_OUT <= transport not SIG_IN after 7 ns

59. 59ECE 545 – Introduction to VHDL Other delay models Rise and Fall delays - a different delay for a transition 0→1 and a transition 1→0

60. 60ECE 545 – Introduction to VHDL Event-driven simulation

61. 61ECE 545 – Introduction to VHDL Event list as a linked list structure time signal new value List of events scheduled to occur at time t q

62. 62ECE 545 – Introduction to VHDL Event list as an array – Timing wheel time signal new value List of events scheduled to occur at time t c

63. 63ECE 545 – Introduction to VHDL Notation (i, v i ’) – an entry of the event list associated with the time t indicating that at the time t the value of signal i is scheduled to be set to v i ’ v(i) – current value at the output of gate i d(i) – nominal delay of gate i

64. 64ECE 545 – Introduction to VHDL Top-level algorithm while (event list not empty) begin t = next time in list process entries for time t end

65. 65ECE 545 – Introduction to VHDL Process entries for time t - Basic version Activated = Ø /* set of activated gates = empty set */ For every entry (i, v i ’) pending at the current time t if v i ’ ≠ v(i) then begin /* it is indeed an event */ v(i) = v i ’ /* update value of signal i */ for every j on the fanout list of i begin update input values of j add j to Activated end For every j  Activated begin vj’ = evaluate(j) schedule (j, v j ’) for time t+d(j) end

66. 66ECE 545 – Introduction to VHDL Event-driven simulation - example (z, 1) 81012 (z, 0) time

67. 67ECE 545 – Introduction to VHDL Notation lsv(j) – last scheduled value of j lst(j) – last scheduled time of j = time of the last event scheduled for signal j

68. 68ECE 545 – Introduction to VHDL Delta delay

69. 69ECE 545 – Introduction to VHDL Delta delay A propagation delay of 0 time units is equivalent to omitting the after clause and is called a delta delay. Used for functional simulation.

70. 70ECE 545 – Introduction to VHDL Two-dimensional aspect of time

71. 71ECE 545 – Introduction to VHDL Top-level algorithm while (event list not empty) begin t = next time in list process entries for time t end If next time in list = previous time then the previous iteration of the loop has advanced time by one delta delay

72. 72ECE 545 – Introduction to VHDL Transactions vs. Events

73. 73ECE 545 – Introduction to VHDL Transaction vs. Event T 5 = T 1 +20 ns Z_OUT transactions Z_OUT events (‘0’, T 1 + 20 ns) (‘1’, T 2 + 20 ns) (‘0’, T 3 + 20 ns) (‘1’, T 2 + 20 ns) (‘0’, T 3 + 20 ns)

74. 74ECE 545 – Introduction to VHDL Properties of signals Signals represent a time-ordered list of values denoting past, present and future values. This time history of a signal is called a waveform. A value/time pair (v, t) is called a transaction. If a transaction changes value of a signal, it is called an event.

75. 75ECE 545 – Introduction to VHDL Signal Attributes

76. 76ECE 545 – Introduction to VHDL Signal attributes (1) S’transaction- a signal of type bit that changes value from ‘0’ to ‘1’ or vice versa each time there is a transaction on S. S’event - True if there is an event on S in the current simulation cycle, false otherwise. S’active – True if there is a transaction on S in a given simulation cycle, false otherwise.

77. 77ECE 545 – Introduction to VHDL Signal attributes (2) S’last_event- The time interval since the last event on S. S’last_active - The time interval since the last transaction on S. S’last_value – The value of S just before the last event on S.

78. 78ECE 545 – Introduction to VHDL Signal attributes (3) S’delayed(T)- A signal that takes on the same value as S, but is delayed by time T. S’stable(T) - A Boolean signal that is true if there has been no event on S in the time interval T up to the current time, otherwise false. S’quiet(T) – A Boolean signal that is true if there has been no transaction on S in the time interval T up to the current time, otherwise false.

79. 79ECE 545 – Introduction to VHDL Detecting setup time violation if clk’event and clk=‘1’ then assert d’last_event >= setup_time report “Setup time violation”

80. 80ECE 545 – Introduction to VHDL algorithmic Design level register-transfer gate transistor layout devices Courses Computer Arithmetic Introduction to VHDL Digital Integrated Circuits Mixed Signals VLSI ECE 545 ECE 645 ECE 586 ECE 699 ECE 681 ECE684 MOS Device Electronics ECE 584 Semiconductor Device Fundamentals VLSI Design Automation ECE 681