Presentation is loading. Please wait.

Presentation is loading. Please wait.

1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU1 PS3xcr Extra Credit Project Modification that can be done to the datapath.

Published byRegina May Modified over 9 years ago

Similar presentations

Presentation on theme: "1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU1 PS3xcr Extra Credit Project Modification that can be done to the datapath."— Presentation transcript:

1 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU1 PS3xcr Extra Credit Project Modification that can be done to the datapath.

2 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU2 Extra Credit  One writeup – 2 parts for extra credit  Each part can raise your final grade 1 ½ %  Part 1 – Add a shifter to the datapath  Part 2 – Beyond integrating a shifter, use the shifter to do integer multiplication (8-bit by 8- bit for a 16-bit result)

3 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU3 The architecture  Block diagram  Dashed line shows interface  Note added control signals and location of shift unit

4 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU4 From the writeup

5 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU5 The operations  Typical shift operations Logical shifts  Left, right Arithmetic shifts  Left and right Rotates left and right with carry and without carry

6 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU6 The writeup continued

7 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU7 Continued  The testbench for this will be on the web and has been modified to include the shift operation.

8 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU8 The second part  This part is a little more challenging  You modify the control by writing a procedure like shiftop to do integer multiplicaiton  The source for the operands are s1reg and s2reg with the result put back in s2reg  You will need a multiply control register for one of the operands which is already set up.

9 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU9 More info from the assignment

10 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU10 cont This is to test your modification

11 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU11 The bus cycle procedure  This procedure runs the busses and internal transfer of data

12 1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU12 Example of use of procedure bus_cycle

Download ppt "1/8/2007 - Extra CreditCopyright 2006 - Joanne DeGroat, ECE, OSU1 PS3xcr Extra Credit Project Modification that can be done to the datapath."

Similar presentations

1/8/2007 - 27 VerilogCopyright 2006 - Joanne DeGroat, ECE, OSU1 Verilog Overview An overview of the Verilog HDL.

1/8/ VerilogCopyright Joanne DeGroat, ECE, OSU1 Verilog Overview An overview of the Verilog HDL.
L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.

L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.
ECE2030 Introduction to Computer Engineering Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers Prof. Hsien-Hsin Sean Lee School.

ECE2030 Introduction to Computer Engineering Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers Prof. Hsien-Hsin Sean Lee School.
Chapter 9 Computer Design Basics. 9-2 Datapaths Reminding A digital system (or a simple computer) contains datapath unit and control unit. Datapath: A.

Chapter 9 Computer Design Basics. 9-2 Datapaths Reminding A digital system (or a simple computer) contains datapath unit and control unit. Datapath: A.
9/15/09 - L14 Functional BlocksCopyright 2009 - Joanne DeGroat, ECE, OSU1 Combinational Functional Blocks & Rudimentary Logic functions.

9/15/09 - L14 Functional BlocksCopyright Joanne DeGroat, ECE, OSU1 Combinational Functional Blocks & Rudimentary Logic functions.
1 ALUs. 2 Topics: ALU Overview - core of the integer datapath - 2 operands, 32-bits wide, plus control signals Exercise: A simple multiplier.

1 ALUs. 2 Topics: ALU Overview - core of the integer datapath - 2 operands, 32-bits wide, plus control signals Exercise: A simple multiplier.
Fall 2005 L15: Combinational Circuits Lecture 15: Combinational Circuits Complete logic functions Some combinational logic functions –Half adders –Adders.

Fall 2005 L15: Combinational Circuits Lecture 15: Combinational Circuits Complete logic functions Some combinational logic functions –Half adders –Adders.
1 Lecture 4: Arithmetic for Computers (Part 4) CS 447 Jason Bakos.

1 Lecture 4: Arithmetic for Computers (Part 4) CS 447 Jason Bakos.
9/15/09 - L25 Registers & Load Enable Copyright 2009 - Joanne DeGroat, ECE, OSU1 Registers & Load Enable.

9/15/09 - L25 Registers & Load Enable Copyright Joanne DeGroat, ECE, OSU1 Registers & Load Enable.
L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.

L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.
1/8/2007 - L24 IEEE Floating Point Basics Copyright 2006 - Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.

1/8/ L24 IEEE Floating Point Basics Copyright Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.
9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexers.

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexers.
1/8/2007 - L24 IEEE Floating Point Basics Copyright 2006 - Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.

1/8/ L24 IEEE Floating Point Basics Copyright Joanne DeGroat, ECE, OSU1 IEEE Floating Point The IEEE Floating Point Standard and execution.
EE694v-Verification-Lect11-1- Lect : The FP adder test plan As noted earlier – there is a difference in black box and while box testing and verificiation.

EE694v-Verification-Lect11-1- Lect : The FP adder test plan As noted earlier – there is a difference in black box and while box testing and verificiation.
1/8/2007 - L3 Data Path DesignCopyright 2006 - Joanne DeGroat, ECE, OSU1 ALUs and Data Paths Subtitle: How to design the data path of a processor.

1/8/ L3 Data Path DesignCopyright Joanne DeGroat, ECE, OSU1 ALUs and Data Paths Subtitle: How to design the data path of a processor.
1/8/2007 - L11 Project Step 5Copyright 2006 - Joanne DeGroat, ECE, OSU1 Project Step 5 Step 2 in behavioral modeling. Use of procedures.

1/8/ L11 Project Step 5Copyright Joanne DeGroat, ECE, OSU1 Project Step 5 Step 2 in behavioral modeling. Use of procedures.
L26 – Datapath ALU implementation

L26 – Datapath ALU implementation
1/8/2007 - L23 Project Step 9 - Sequential Machine Copyright 2006 - Joanne DeGroat, ECE, OSU1 Project Step 9 Beyond the ALU and Datapath. Sequential Machine.

1/8/ L23 Project Step 9 - Sequential Machine Copyright Joanne DeGroat, ECE, OSU1 Project Step 9 Beyond the ALU and Datapath. Sequential Machine.
1/8/2007 - L7 Project Step 3Copyright 2006 - Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement.

1/8/ L7 Project Step 3Copyright Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement.
9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

Similar presentations

Ads by Google