1. Escola Tècnica Superior d’Enginyeria de Telecomunicació de Barcelona
UNIVERSITAT POLITÈCNICA DE CATALUNYA
Design & analysis of a 2.4 GHz CMOS Quadrature VCO using AMSS35D4 technology
RFSoC – Final Project
Master in Electronics Engineering
Josep Maria Margarit Taulé
Advisor: Xavier Aragonès Cervera

2. 1 Introduction 2 Design procedure 3 Results 4 Conclusion

3. 1 Introduction 2 Design procedure 3 Results 4 Conclusion

4. Introduction Design procedure Results Conclusion
Complete design procedure of a 2.4 GHz LC CMOS quadrature VCO.
Process technology: AMSS35D4 (SiGe 0.35 m, 4-metal, thick metal available).
Tasks:
Initial rough calculations
Accurate cadence rf-modelled simulation and tuning
Result analysis and conclusions

5. 1 Introduction 2 Design procedure 3 Results 4 Conclusion

6. Specs Spec Units Value Vdd V 3.3 Power consumption mW <25
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Specs
Spec
Units
Value
Vdd V
3.3
Power consumption mW
<25
Output load
k,pF f0
GHz
2.4
Tuning range
MHz
100
Harmonic distortion
dBc
<-40
S.E. output amp.
1 Vpp ± 15%
Phase noise
<-100
Phase error
<1

7. Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Handy calculations
First order, simplified expressions from subject topics
Automatic calculation procedure
Excel worksheet

8. Single VCO (L selection)
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Single VCO (L selection)
Thick metal (higher Q)
Large L/Q desired: less power consumption

9. Single VCO (varactor selection)
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Single VCO (varactor selection)
Minimum varactors
Higher QT

10. Single VCO (Itail calculation)
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Single VCO (Itail calculation)
Losses estimation:
Itail must be:

11. Single VCO (nmos W-L choice)
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Single VCO (nmos W-L choice)
From previous Itail calculation (b=2):
But... Transistor losses!
gds, gmb
L=1 µm
Further considerations:
Adjustments Iterative tran simulations

12. Single VCO Itail =7 mA gm=13 mS W=75 µm L=1 µm
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
Single VCO
Itail =7 mA
gm=13 mS
W=75 µm
L=1 µm

13. QVCO Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
QVCO

14. QVCO (coupling definition)
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
QVCO (coupling definition)
Coupling factor:
Trade-off:
α Phase noise , but phase error !! α =1/3

15. QVCO (center frequency tuning)
Introduction Design procedure Results Conclusion
Specs Calculations Single VCO QVCO
QVCO (center frequency tuning)
Pss simulations
From an initial frequency (f0i):
Cpoly resizing
~350 fF

16. 1 Introduction 2 Design procedure 3 Results 4 Conclusion

17. Results (I-Q transient analysis)
Introduction Design procedure Results Conclusion
I-Q tran F/V Harm./Ph. noise Ph. error Summary
Results (I-Q transient analysis)
Vtank ~ 900 mV
Tinit ~ 1.5 µs

18. Results (f/V pss analysis)
Introduction Design procedure Results Conclusion
I-Q tran F/V Harm./Ph. noise Ph. error Summary
Results (f/V pss analysis)
ftun ~ GHz
KVCO ~ 268 MHz/V

19. Results (harmonic/phase noise analysis)
Introduction Design procedure Results Conclusion
I-Q tran F/V Harm./Ph. noise Ph. error Summary
Results (harmonic/phase noise analysis)
Max. Harm. level ~ dBc
Phase noise (600 kHz) ~ -118 dBc

20. Results (phase error) Phase error:
Introduction Design procedure Results Conclusion
I-Q tran F/V Harm./Ph. noise Ph. error Summary
Results (phase error)
Phase error:

21. Results (summary) QVCO final parameters QVCO final results
Introduction Design procedure Results Conclusion
I-Q tran F/V Harm./Ph. noise Ph. error Summary
Results (summary)
QVCO final parameters
QVCO final results

22. 1 Introduction 2 Design procedure 3 Results 4 Conclusion

23. Introduction Design procedure Results Conclusion
Complete design procedure of a 2.4 GHz LC CMOS quadrature VCO (SiGe 0.35 m, 4-metal, thick metal tech process)
Tech. main drawback: low QL Itail
Design key points:
L selection (highest L-Q at main frequency)
But... Ctotal>Cparasitics!!
gds to be considered!
Coupling factor trade-off (Phase noise vs. Phase error)

24. Escola Tècnica Superior d’Enginyeria de Telecomunicació de Barcelona
UNIVERSITAT POLITÈCNICA DE CATALUNYA
Design & analysis of a 2.4 GHz CMOS Quadrature VCO using AMSS35D4 technology
RFSoC – Final Project
Master in Electronics Engineering
Josep Maria Margarit Taulé
Advisor: Xavier Aragonès Cervera 24