1. CS-EE 481 Spring 2004 1Founder’s Day, 2004 University of Portland School of Engineering Project Steelhead A CMOS 4-Bit x 4-Bit Multiplier Authors Scott Sato Ross Yoshioka Advisor Dr. Osterberg, Dr. Lillevik Industry Representative Mr. Michael M. DeSmith Intel Corporation

2. CS-EE 481 Spring 2004 2Founder’s Day, 2004 University of Portland School of Engineering Agenda Introduction Ross Yoshioka Background/Demonstration Ross Yoshioka Methods Ross Yoshioka Results Scott Sato Conclusions Scott Sato

3. CS-EE 481 Spring 2004 3Founder’s Day, 2004 University of Portland School of Engineering Introduction Dr. Osterberg, Dr. Lillevik, Michael DeSmith, Sandy Ressel, and Dr. Lu for your countless advice and support! ! ! -Solves the Problem of Serial Multiplication of two 4-bit binary numbers (0-15 in Decimal). -Used as a Demo for Future Students - Answer sent out in 8-bit binary, converted to decimal equivalent (Highest Value = 225) - Learn the general workings of how to design and create a 4- bit x 4-bit Serial Multiplier.

4. CS-EE 481 Spring 2004 4Founder’s Day, 2004 University of Portland School of Engineering Background/Demonstration 1. Turn the 2 Rotary Devices on Our Input Pad 2. Both Numbers are Displayed on the Red Displays in Decimal Form 3. Press the Clear than the Equal Button 4. Answer Shows up in Decimal Form on Green Display.

5. CS-EE 481 Spring 2004 5Founder’s Day, 2004 University of Portland School of Engineering Methods 1. Designed the MOSIS chip using B²Logic (D-Flip Flops, Combinational Logic, etc.) 2. Converted B²Logic File to TPR File 3. Designed the Logic behind the input and output devices (GAL’s/ABEL, BCD-to-7-Segment Decoders, etc.) 4. Created Macro Model and System Model 5. Replace Macro Model with MOSIS chip

6. CS-EE 481 Spring 2004 6Founder’s Day, 2004 University of Portland School of Engineering B²Logic Simulation

7. CS-EE 481 Spring 2004 7Founder’s Day, 2004 University of Portland School of Engineering Results (Top Level Diagram)

8. CS-EE 481 Spring 2004 8Founder’s Day, 2004 University of Portland School of Engineering Block Diagram

9. CS-EE 481 Spring 2004 9Founder’s Day, 2004 University of Portland School of Engineering Chip Block Diagram

10. CS-EE 481 Spring 2004 10Founder’s Day, 2004 University of Portland School of Engineering Output Decoder Diagram

11. CS-EE 481 Spring 2004 11Founder’s Day, 2004 University of Portland School of Engineering B²Logic Simulation

12. CS-EE 481 Spring 2004 12Founder’s Day, 2004 University of Portland School of Engineering TPR File

13. CS-EE 481 Spring 2004 13Founder’s Day, 2004 University of Portland School of Engineering

14. CS-EE 481 Spring 2004 14Founder’s Day, 2004 University of Portland School of Engineering Conclusions -Demonstrated the Design of a CMOS Multiplier: -B2Logic Simulation -TPR File Creation -I/O System Design and Implementation -Integration of the Prototype’s Parts -Keep on schedule throughout the Design Process -Checking and Rechecking the TPR. File Until it is Absolutely Correct -In the future, maybe even use BLT (Project Pitroach)