1. Update on Simulation and Sensor procurement for CLICPix prototypes Mathieu Benoit

2. Outline Possible prototype – HV-CMOS with Ivan Peric – VTT Active edges sensors – Microns/MPI HLL sensor – Sensor processing (Thinning) Simulation – CLICpix model – Deployement to lxbatch – Digitization strategy – Some results

3. Prototypes Timepix3 not available before the end of next year We can take advantage of the common footprint for medipix1,2,3 and timepix1,3 to begin thinking about producing sensors to study various properties – Various thickness – Implant size

4. Varying implant width Pulse risetime, charge sharing can vary according to E Field distribution in pixel cell

5. VTT Sensor production

6. Edge processing

7. VTT Summary Characteristicsvalues Thickness(es)50 – 500 um Wafer size(s)6 ’’ ProcessSingle/double sided Wafer type(s)P(10kOhm) FZ, N(7kOhm) FZ Edge characteristics50-100um pixel to edge distance using active edge technology

8. HV-CMOS Active diodes ATLAS is planning a MPR in 180nm process for HV-CMOS sensors – Total run cost : 157k€ 28 masks (6 Metal layers, MiM Capacitor, deep- nwell) : 126k€ 8x 8’’ wafers 19.8k€ Die size 21 x 21 mm Ivan has agreed that a medipix-like structure could be planned in the production, but would only cover part of the timepix chip – Detection diode + Preamplifier – Capacitive coupling (glue) Possibility to do sub-pixelisation (ATLAS like) – Sub-pixels with different gain and pedestal – Pixel ID is determine from ToT Value Pros Thin depleted depth allows for thinning without paying in Signal to noise ratio Capacitive coupling (no bump bonding) Some intelligence can be put on sensor Cons Gluing procedure need test with thin structure, with sensor smaller than chip (UMB bumps present?) Preamp power need to be provided to sensor New PCB, double sided wire bonds Glue might not be mechanically reliable, or radiatino hard

9. Timepix : 14.08x14.08mm active area 16.120mm x 14.111mm total area HV-CMOS : 4x2mm chip, bonding 1mm from chip edge Timepix balcony Active area HV-CMOS

10. Microns Semiconductors Possibility to do dedicated run or to participate with UK partners in MPR Experience with Microstrips for D0, PHENIX, BRAHMS, HERMES, LHCb VELO Experience with ATLAS FE- I3 and FE-I4 pixel sensors

11. MICRONS Summary Characteristicsvalues Thickness(es)3’’-> 15-500 um 4 ’’->15-2000 um 6’’->100->2000 um Wafer size(s)3’’, 4’’, 6’’ ProcessSingle/double sided Wafer type(s)P,N FZ, MCz Edge characteristicsGuard ring structures (100-500 um) + dead edges (50-200 um)

12. MPI HLL MPI HLL developped a process to produce thin sensor (75um) produced in house. First experience with thin strip sensor encouraging https://indico.cern.ch/getFile.py/access?contribI d=14&sessionId=4&resId=0&materialId=slides&c onfId=114255 https://indico.cern.ch/getFile.py/access?contribI d=14&sessionId=4&resId=0&materialId=slides&c onfId=114255 SLID interconnect technology also available Possibility of MPR unknown, but feasable with adequate input of money

13. Thinning (Chip)

16. Thinning (Sensor) Sensor thinning is more delicate – Each side need a mirror polish finish (grinding, then 9um grain, 3um grain, 1 um grain, colloidal solution (Nalco) ) 3 possible approaches – With junction Backside implantation done prior to thinning (Ohmic contact) Thinning and polishing do outside fab (Rockwood) Wafer get back to fab for frontside processing – Epi wafers (ALICE) Wafer front processed Epi layer etched except for the last few microns forming a ohmic contact with a deposited metal layer – SOI wafers Wafer front processed Oxide etched away and backside processed (after bump bonding)

17. Timepix availability Not clear if timepix chips are still available Michael Campbell was contacted to inquire on possibilities, waiting for the answer back

18. SIMULATION

19. GEANT4 simulation + digitization The software was ported to lxbatch system allowing large scale production – Python script to generate sim template and launch prod and analysis Possibility now to scan pixel size, thickness, incident angles, beam type and energy Produced some preliminary analysis with 20x20um pixel, 50 um thickness Some Geometry handling bugs to be solved, timing needs to be added in the digitizer/ handled in the framework

20. Digitization for HV-CMOS I started to look at how to include in the simulation for a digitizer for HV-CMOs type sensor but information is limited Reiterated emails around to get access to TCAD software (IT Dept, RD50, Electronics Depth)

21. Full detector Simulation Digitizer Clustering + Hit reconstruction ILCsoft reconstruction etc.Residuals, efficiency dE/dX ?

22. Conclusion Many possibilities to produce CLIC like prototypes for next year Availability of readout chips an issue Simulation ongoing, some bug need to be fixed in clustering, geometry, but the machinery is there to produce large scale studies, TB simulation