1. Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder

2.  Introduction  Design Methodology  Schematic Diagram  Simulated Result  Layout  Conclusion

3. 4-bit Parallel Full Adder

4. 4-bit Parallel Full Adder Binary Addition and Operation

6. In our full adder design, we are using the 0.35 µm CMOS technology. So the length of the transistor we fixed to 0.35 µm. L = 0.35 µm The default ratio of W to L W/L = 3 So, we design the width of the NMOS 2.5 times its length WN = 0.35 µm x 3 = 1.05 µm As the width of the PMOS is 2 times the width of NMOS, hence WP = 1.05 µm x 2 = 2.1 µm

7. Schematic Diagram of Full Adder

8. Schematic Diagram of 4-bit Parallel Full Adder

9.  Output for First Block

10.  Output for Second Block

11.  Output for Third Block

12.  Output for Fourth Block

13. Power Dissipation As temperature increases, power dissipation increases Temperature, o CPower Dissipation, W 03.7083m 275.0536m 9512.081m

14.  Propagation Delay  Proportional  As the temperature increases, the propagation delay increases  Due to degradation of carrier mobilities when the temperature is increased. Temperature (°C) Rising edge delay (ps) Falling edge delay (ps) 0-13.232-4.3647 9527.830010.8075

15. Layout of One Full-Adder Block

16.  Same transistor types are grouped together  less complex design.  To reduce the total size occupied.  reduce power consumption.  The rule of thumb technique  reduce the collision between metal routings and to reduce the complexity during top-level design.

17.  Transistor count: 112 (28 per full adder circuit)  Layout area: 163.4µm x 227.1µm  Power dissipation (27 o C): 5.0536mW

18.  In conclusion, the schematic designed in this project is acceptable, at which the performance and delay is under reasonable range. The design can be considered as successful, due to the adequate precision and low power consumption. Future improvement on the current design is possible to achieve higher performance.