1. A Low-Power Precomputation-Based Parallel CAM Chi-Sheng Lin, Jui-Chang, Bin-Da Liu IEEE2003

2. Outline Intro CAM Design concept of PB-CAM Circuit Design of PB-CAM Improved PB-CAM Experimental Results Conclusion Conclusion

3. Intro Parallel CAM function is used widely lookup tables, databases, associative computing, data compression, etc. It need large power to achieve parallel CAM

4. CAM

5. Design concept of PB-CAM To reduce the comparison between input and the stored data. Add parameter extractor, parameter memory.

6. Design concept of PB-CAM

7. With an m words by n bits CAM size PB-CAM: 1th comparison: m*upon[log(n+2)] 2th comparison: (m*n)/(n+1) Total=1th+2th CAM: Total=M*(upon[log(n+2)+1])

8. Design concept of PB-CAM

9. Circuit Design of PB-CAM Traditional dynamic CAM: 1) The dynamic circuit needs an extra precharge time for each data searching operation. 2) The dynamic circuit has some problems, such as charge sharing and noise problems. 3) A clock signal is necessary to handle the circuit operation. 4) The noise margin of dynamic circuit is less than.

10. Traditional dynamic CAM

11. Circuit Design of PB-CAM static pseudo-nMOS circuit a) In the data searching operation, if the valid bit is invalid(v=1), then the PM1 is turned off and the NM1 is turned on. b) Otherwise, PM1 is turned on, and NM1 is turned off.

12. pseudo-nMOS circuit

13. Circuit Design of PB-CAM Another problem of pseudo-nMOS circuit.  power dissipation With an m-words CAM size input data only matches one stored data per data searching operation. m-1 data mismatching between stored data and input data per data searching operation.

14. Circuit Design of PB-CAM

15. parameter comparison circuit is used to control the pull-up PM1. Therefore, the number of PB-CAM word circuits that consume static power is reduced to ((m/n-1)-1).

16. Circuit Design of PB-CAM Traditional CAM cell is constructed by typical nine-transistor six-transistor SRAM cell to store a data bit, an XOR-type comparison circuit containing two nMOS transistors, and an nMOS pull-down device to drive the word match line

17. Circuit Design of PB-CAM

18. Proposed PB-CAM cell five-transistor D-latch device to store a data bit and a NAND-type comparison circuit containing two nMOS transistors to drive the word match line. To achieve low-voltage operation, the feedback inverter (INV2) is a weak-driving design to allow the input data(BL) to be stored in the D- latch device easily.

19. Circuit Design of PB-CAM

20. Advantage: 1. Searching time is better 2. Simplifies HW design 3. reduces operating voltage Disadvantage 1. Access performance is poorer

21. Improved PB-CAM Because of the parameter extraction function lot difference between probability of parameters.

22. Table of 14 bits ones-count parameter extractor

23. Block XOR approach

25. Table of 14 bits Block XOR PB- CAM

26. Experimental Results

29. Conclusion Based on the precomputation methodology, the circuit reduces most of the comparison operations and transistors to achieve low-power, low-cost, and low- voltage features.