1. LOW VOLTAGE OP AMPS We will cover: –Low voltage input stages –Low voltage bias circuits –Low voltage op amps –Examples Methodology: –Modify standard circuit blocks for reduced power supply voltage –Explore new circuits suitable for low voltage design

2. ITRS Projection – near term

3. ITRS Projection – longer term

4. Low-Voltage, Strong-Inversion Operation Reduced power supply means decreased dynamic range Nonlinearity will increase because the transistor is working close to V DS(sat) Large values of λ because the transistor is working close to V DS(sat) Increased drain-bulk and source-bulk capacitances because they are less reverse biased. Large values of currents and W/L ratios to get high transconductance Small values of currents and large values of W/L will give smallV DS(sat) Severely reduced input common mode range Switches will require charge pumps

5. Input common mode range drop V DD – V DS3sat + V T1 > v icm > V DS5sat + V T1 + V on1 1.25 -0.25 + 0.75 > v icm > 0.25+0.75+0.25, unsymmetric!

6. p-n complementary input pairs n-channel: v icm > V DSN5sat + V TN1 + V onN1 p-channel: v icm <V DD - V DSP5sat - V TP1 - V onP1

7. Non-constant input g m N

8. constant input g m solution Let Vb1 depends on Vicm so that Mb1 is turned on when MN1,2 are turned off, and Ip becomes 4 times. Similarly when MP1,2 are off, In becomes 4 times. When both pair on, In and Ip are bothe 1 times

9. Set VB1 = Vonn and VB2 = Vonp

10. Rail-to-rail constant g m input As Vin+ and Vin- reduce, MN1,2 begins to turn off, MNC1,2 also begins to turn off. I7 reduces, so does I8. I9 = I12-I8 increases, so does I10, which is 3(I12-I8)=3(Ip-In), which becomes 3Ip when n-pair turns off. When both on, I5=I1=I12=IBP=Ip; I11=I7=I6=IBN=In

11. V i+ V i- Complementary input stage with rail-to-rail Vicmr and constant g m V i+ V i- 3:   :3 V i- V i+ IpIp InIn 3(I p -I n ) IpIp InIn InIn V bp V bn IpIp 3(I n -I p ) InIn IpIp  (I p -I n )  (I n -I p ) i n+ i n- i p+ i p- N1N2P1P2PC1,2 NC1,2 BN BP 1234

12. V o1+ V o1- Folded cascode stage: summing current and convert to voltage i n+ i n- i p+ i p- -i n+ -i p- i o1- =i p- - i n+ i n+ =+g mn1 *v id /2 i n- = -g mn1 *v id /2 i p+ =+g mp1 *v id /2 i p- = -g mp1 *v id /2 i o1- =i p- - i n+ = -(g mp1 +g mn1 )*v id /2 i o1+ =i p+ - i n- = (g mp1 +g mn1 )*v id /2 V o1- = i o1- /g o1 V o1+ = i o1+ /g o1 V o1d = (V o1+ - V o1+ ) = v id *(g mp1 +g mn1 )/g o1 V xx V yy V zz V bb

13. Folded cascode stage: feedback to reduce go1 V xx V yy V zz M1 M2a M2b V bb M3 M4 i g mn1 v d /2 g dsn1 g ds4 g ds3 v cp v cn g ds1 g ds2a g ds2b g m2a v cn +g mb2a v cn g m2b v cn +g m2b v cp +g mb2b v cn v o1+ g m3 v cp Show that it is possible to make gain (vo1/vd) infinity by proper sizing.

14. Folded cascode stage: feedback to reduce go1, alternative V xx V yy V zz M1a M2 M1b V bb M3 M4 i g mn1 v d /2 g dsn1 g ds4 g ds3 v cp v cn g ds1 g ds2 g ds1b g m2 v cn +g mb2 v cn g m1b v cp v o1+ g m3 v cp

15. In either case, you can set vd=0, write KCL’s for the vn, vn and vo1 nodes, eliminate vn and vp, obtain expression in vo1 alone, set coefficient to zero, this gives conditions for go=0. From that, you can solve for gm for the feedback transistor and see how that can be realized. For example, in the first choice, if you make gds of M1 and M3 4 times as large as the other transistors, it becomes relatively simpler to meet the conditions. Small signal analysis for 2 nd choice is easier, but quiescent voltage a concern. You can also feedback to PMOS transistors. Feeding back to top or bottom transistors faces big challenges when supply voltage increases. If the whole M2 (or M3 in the P version) is controlled by feedback, then the VgsQ of M2 is independent of supply.

16. M1 V G3 V G2 M1 M3 M2     M4 M3 M2     M4     Regulated Cascode for gain improvement V xx V zz k VDVD VSVS VSVS VDVD VGVG VGVG If you regulate, you have to regulate all four.

17. Second stage V xx V yy V zz M1 M2 M6 V bb M3 M4 M7

18. Second stage push pull: Monticelli style V xx V yy V zz M1 M2 M6 V bb M3 M4 M7 Requires: VDD-VSS > Vgs6+Vgs7+Vdssat_floating_CS VbpVbn D. M. Monticelli, “A quad CMOS single-supply Op Amp with rail-to-rail output swing,” IEEE J.Solid-State Circuits, no. 6, pp. 1026–34, Dec. 1986.

19. Don’t do V xx V yy V zz M1 M2 M6 V bb M3 M4 M7 Unpredictable current in second stage

20. Vzz Vbn Vxx Vbp So, Vg6Q = Vzz This sets Id6.Q So, Vg7Q = Vxx This sets Id7Q. These circuits can come from the same biasing circuit for the main amplifier. So, no extra current, power consumption, noise, and offset introduced.

21. g ds4 g ds3 g ds1 g ds2a g m2a v cn +g mb2a v cn v o1+ g m3 v cp Floating CS do not change ro1 or DC gain g dsn g dsp g mn v o1+ -g mp v’ o1+ V’ o1+ The impedance looking down from Vo1+ is Rn To find impedance looking up from Vo1+, inject a test current i up. V’ o1+ = i*Rp i_g dsn/p = (i-g mn v o1+ +g mp v’ o1+ ) V o1+ =V’ o1+ + i_g dsn/p /(g dsn + g dsp ) V o1+ =i*Rp+(i-g mn v o1+ +g mp i*Rp) /(g dsn +g dsp ) V o1+ (1+g mn /(g dsn +g dsp )) =i*{Rp[1+g mp /(g dsn +g dsp )] +1/(g dsn +g dsp )} V o1+ /I =Rp g mp /g mn RnRn RpRp So, size them so that g mp ≈ g mn Note: gmn and gmp include possible body effects.

22. To the two gate terminals of M6 and M7, the two floating CS appears as a voltage source providing a voltage offset between the gates. The impedance seen by the two gate terminals can be calculated by: Rs = (Vgp – Vgn)/(current through the floating CS) = (Vgp – Vgn)/(gmp*Vgp – gmn*Vgn + (Vgp – Vgn)*(gdsn+gdsp)) ≈ 1/(gmp + gdsn+gdsp) ≈ 1/gmp The above assumed that the NMOS and PMOS are sized to have the same gm. Also, the calculation is only valid when both NMOS and PMOS are fully on and both in saturation. When Vo is experiencing large swings, these conditions are not met. And the voltage difference between the two gate terminals no longer remain constant.

23. Differential signal path compensation V xx V yy V zz M1 M2 M6 V bb M3 M4 M7

24. In order for M6 and M7 to have well defined quiescent current, we have to bias the circuit so that at Q, Vd2 = Vzz. This is naturally provided by the usual bias generator: Vzz Vbb Problem: Vd2 is a high impedance node, small current mismatch in M1 and M4 leads to significant voltage change at vd2, which in turn changes the biasing current in the output stage. Solution: use feedback to stabilize common mode of Vd2.

25. Vzz Vd2LVd2R Feedback to M4 or part of it Since Vd2L and Vd2R are normally nearly constant. We do not need to worry about the input range accommodation for this circuit. Size the circuit so that, when v id =0, Id6 remain near desired level over all process variations in M1 and M4.

26. Current sensors Quiescent biasing IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998

28. Vo+ and Vo- also need common mode stabilization M6 M7 V ocmd M7t M7t’s are in triode Choose R to a couple times bigger than Ro Choose C to be near or a couple times larger than Cgs of CMFB circuit. R R CC

29. M6 M7 V ocmd M7t M7t’s are in triode R R CC Insert these

30. Why RC in common mode detector V1 V2 R R Cgs V KCL at V: (V1 – V)/R + (V2 – V)/R = V * sCgs (V1 + V2)/R = V(sCgs + 2/R) V = (V1 + V2)/2 * 1/(1 + sRCgs/2) When |s| =|jw| << 2/RCgs, V ≈ (V1 + V2)/2 Otherwise V is not close to common mode To have CM detector work up to GB, R << 2/(2  GB*Cgs)

31. Why RC in common mode detector V1 V2 R R Cgs V KCL at V: (V1 – V)(1/R +sC) + (V2 – V) (1/R +sC) = V * sCgs (V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC) V = (V1 + V2)/2 * (1 + sRC)/(1 + sRC + sRCgs/2) As long as Cgs/2 < C, at all freq: V ≈ (V1 + V2)/2 C C Hence, the RC network acts as a better CM detector

32. Why CMBF to M7t instead of first stage: Vo1+ Vo1- Vo+ For CM behavior, assume DM=0. Vo1+=Vo1-, and Vo+=Vo-=Vocm. Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level. With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level. Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended. Vg

33. Compensation for diff signal path closed-loop stability V xx V yy V zz M1 M2 M6 V bb M3 M4 M7 C C

34. At relatively low frequency: Because of gain from Vo1 to Vo, small signal Vo1 is much smaller than small signal Vo. Small signal current in compensation network is approximately Vo/(1/gmz+1/sCc). This current is injected to the Vo1 node. Alternatively, a similar current can be injected: Impedance looking into a cascode node is about 1/gm Connecting Cc to a cascode node generates a current of the form Vo/(1/gm +1/sCc) Because the base transistor is a current source, this small signal current goes to the Vo1 node Even at high frequency, the current form is still valid.

35. Alternative compensation V xx V yy V zz M1 M2 M6 V bb M3 M4 M7 C C

36. In the Cc+Mz connection, Bias voltage of Mz can be matched to track bias voltage of M6  robustness to process and temperature variations Size of Mz can be parameter scanned so as to place zero to cancel the secondary pole of the amplifier In the Cc to cascode connection, Bias voltage can still be derived using current mirrors from a single current source,  still have process and temperature tracking But size of cascode transistor is determined based on folded cascode stage design Cannot arbitrarily choose its size without considerations for output impedance at Vo1, gain of op amp, and so on.

37. Alternative compensation V xx V yy V zz M1 M2 M6 V bb M3 M4 M7 C C

38. Vicm Vo+, Vo- Use open loop Vicm sweep to find a “sweet spot” for your Vicm

39. Vicm Vin Vo+ With Vicm at “sweet spot”, sweep Vin near Vicm with very fine steps (uV) Vin Vo- d(V o+ -V o- ) dV in V o+ -V o- V in

41. V b2 V CMFB V b1 C V o+ V o- V o+ V o- Folded cascode stage: summing current and convert to voltage V i- 3:1

42. Summing circuit to add n-signal and p-signal together

43. Rail-to-rail constant g m input Coban and Allen, 1995

44. The composite transistor

46. Bulk-Driven MOSFET

47. Bulk-Driven, n-channel Differential Amplifier I1=I2=I5/2 As Vic varies, V d5 changes and g mb varies  Varied gain, slew rate, gain bandwidth; nonlinearity; and difficulty in compensation

48. Bulk-driven current mirrors Increased vin range and vout range

49. Traditional techniques for wide input and output voltage swings 1 Io = Iin+Ib Iin Ib 1 1 1 1/4 V T +V on V T +2V on V on >2V on + – V T +V on

50. Traditional techniques for wide input and output voltage swings 1 Io Iin Ib 1 1 1/4 V T +V on V T +2V on V on >2V on + – V eb Io = Iin

51. A 1-Volt, Two-Stage Op Amp Uses a bulk-driven differential input pair, wide swing current mirror load, and emitter follower level shifter

52. Op Amp Performance

53. Frequency Response

54. Low voltage VBE and PTAT reference

55. Threshold Voltage Tuning for low power supply voltages operation

56. Implementation of the voltage sources

57. A low voltage Op Amp core

58. Op Amp Implementation Clock boosterBias voltage generator

59. Clock booster (doubler) C B1 >> C BL

60. Experimental Results Power supply750mV Slew Rate3.1V/uS GB3.2MHz DC gain62dB Input offset voltage2.2mV Input common mode range0.1V-0.58V Output swing for linear operation0.31V-0.58V PSRR at DC82dB CMRR at DC56dB Total power consumption38.3uW

61. Common mode feedback for low voltage

62. 1.5v op amp for 13bit 60 MHz ADC

63. Output Stage and CMFB

64. Folded cascode with AB output Lotfi 2002

65. Simulated performance 0.25 um process 1.5 V power supply 82 dB DC gain 2 V p-p diff output swing 170 MHz UGF @ 10 pF load 77 o PM with  = 1/5 0.02% 1V step settling time: 8.5 ns Full output swing Op Amp power: 25 mW

66. Differential difference input AB output Alzaher 2002

67. Nested Miller Cap Amplifier Not much successes

68. Low voltage amp

70. LOW POWER OP AMPS Op Amp Power = (VDD-VSS)*Ibias –Reduce supply voltage: effect is small Many challenges in low voltage design same as before –Reduce bias: factor of hundred reduction Weak inversion operation Nano-amp to small micro-amp currents Needs small current biasing circuits and small current reference generators Needs output stage to drive the load –Design it so that it consume tiny quiescent power –But generate sufficient current for large signals –Tradeoff speed for reduced power

71. Sub-threshold Operation Most micro-power op amps use transistors in the sub-threshold region. n p ~1.5; n n ~2.5

72. Two-Stage, Miller Op Amp in Weak Inversion At VDD-VSS=3V, ID5=0.2uA, ID7=0.5uA, got A=92dB, GB=50KHz, P=2.1uW

73. Push-Pull Output in Weak Inversion First stage gain Total gain S=W/L

74. Increasing gain gogo Gain=gm/go What is V ON ? L 5 =L 12, W 12 =W 5 /2 S 13 <<S 4

75. Increasing I out with positive feedback When v i1 >v i2 i 2 >i 1 i 26 =i 2 -i 1 >0 i 27 =0 i 28 =A*i 26 i tail =I 5 +i 28 =i 1 +i 2 i 2 /i 1 =e (vi1-vi2)/nvt =e vin/nvt i 2 =i 1 e vin/nvt I 5 + A*(e vin/nvt -1)i 1 = (e vin/nvt +1)i 1 i 1 =I 5 /{A+1-(A-1)e vin/nvt )}

76. A=0 is normal case A > 0 can greatly enhance available output current for load driving

77. A=0 A=1 A=2 A=3 i1 i2 i 1 =i 2 i 2 =i 1 e vin/nvt as v in  I5 i 1 +i 2 =I 5 New i1+i2 i 1 +i 2  much faster than i 2 -i 1 

78. DC Offset (Self-mixing) A D A D  c 0

85. Fully differential, with DC gain >= 90 dB, GB>=50MHz, CL=2p on each side, slew rate >= 100V/us, small signal step response (closed-loop with inverting |gain|>=1) overshoot <= 10% and 0.1% settling time <=75ns. (these are nearly the same as op amp 1) Now the goal is to minimize total quiescent current. The following becomes much tougher: Total quiescent current budget must be at least 10 times smaller. Output differential swing must be near rail to rail Input common mode range must cover rail to rail Vdd – Vss can change from 5 V all the way down to 2.2 V. Most of the specs should remain nearly constant over ICMR and over Vdd

86. Strategies for rail to rail ICMR Complimentary input: Vbc + Veb1  Vdd – Vdsat5 + Vth1 Vss + Vdsat9 – Vth3  Vbbc – Veb3 Total range: Vss > Vss + Vdsat9 – Vth3  Vdd – Vdsat5 + Vth1 > Vdd Need: Vbc +Veb1 <= Vbbc – Veb3 for all Vdd

87. Dual n-channel input for PVT-R IiIi I fc Vbc + Veb1  Vdd – Vdsat5 + Vth1 Vss  Vbc + Veb1 Vins+ and Vins- are shifted up by about Vbc + Veb1=Vthn+Veb13+Veb13c+Veb2

88. Here: Vins+ and Vins- are shifted up by Vthp+Veb5, which can be made to be about Vthn+Veb13+Veb13c+Veb2

89. Level Shifter Analysis Transfer Function Pole Zero Model Since |p|<|z|, there is phase delay. Delay is max at sqrt(pz). To make delay small enough, need |p| >> UGF of A . So make gm large, and Cgs large relative to CL. What is RL? What about gmb effect?

90. When Vin+ and Vin- are high, MS3 and MS4 are fully on. All the current in MS3&4 are mirrored to MS6. MS7 will have 0 current, so does MS8. That turns off the shift-input pair. As Vin+- drop, the right tail current source is pushed into triode. I_MS5 decreases, I_MS7 increases, and the shift-input pair is being turned on. The transition range depends on Veb of tail cascode and of input pair. When both pairs are partially on, there is no high impedance node.

91. Will this addition make the drain of MS6 always low impedance? Current in this needs to be increased to accommodate the added current

92. Will this work?

93. Push-pull output IoIo I o /M 1:M Main goal: make Vo swing from Vss to Vdd. Equivalent to double the output stage gm,  ↑gain, GB Make slew rate higher than I o /C L Make output Vebo small. When Vo1 swings, say by 2.1Vebo, I CL can be 10xI o ! But quiescent Io depends on Vo1Q, and uncontrolled.

94. IoIo I o /M 1:M I o /M I tail 1:1 match Output quiescent current control by local CMFB. Vo1 CMFB

95. M1a+M1b forms diff pair with M2 Vo1+/- swing is about +- 2.# * Vebo, or about +- 0.3 to 0.4 V, so M1a and M1b should have Veb about equal to 2*Vebo. Vb3 should be selected so that M12 is still in saturation when Vo1 drops to a little below Vthn-Vebo. The Veb of M12, M10, and the size of diode connected CMFB1 transistor should be such that M 10 is guaranteed to be in saturation. Note that there is only one high impedance node (Vo1 node) in this CMFB loop, hence the loop UGF can be made high and still maintain good stability.

96. Vo+ and Vo- also need common mode stabilization M16 M21M17 V ocmd M21tM17t M17t and M21t are in triode Choose R to a couple times bigger than Ro Choose C to be near or a couple times larger than Cgs of CMFB circuit. R R CC M15 M18 M19 M20

97. V ocmd R R CC M:1 1:M M:1 V xx

98. Why RC in common mode detector V1 V2 R R Cgs V KCL at V: (V1 – V)/R + (V2 – V)/R = V * sCgs (V1 + V2)/R = V(sCgs + 2/R) V = (V1 + V2)/2 * 1/(1 + sRCgs/2) When |s| =|jw| << 2/RCgs, V ≈ (V1 + V2)/2 Otherwise V is not close to common mode To have CM detector work up to GB, R << 2/(2  GB*Cgs)

99. Why RC in common mode detector V1 V2 R R Cgs V KCL at V: (V1 – V)(1/R +sC) + (V2 – V) (1/R +sC) = V * sCgs (V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC) V = (V1 + V2)/2 * (1 + sRC)/(1 + sRC + sRCgs/2) As long as Cgs/2 < C, at all freq: V ≈ (V1 + V2)/2 C C Hence, the RC network acts as a better CM detector

100. Why CMBF to M17t instead of first stage: Vo1+ Vo1- Vo+ For CM behavior, assume DM=0. Vo1+=Vo1-, and Vo+=Vo-=Vocm. Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level. With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level. Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended. Vg

101. Current budgeting SR >= dVo/dt = 2*dVo+/dt At slewing: dVo+/dt = I_CL / CL. Let Io_slew = SR * CL /2. So we need Iomax > Io_slew. If Iomax can be as high as K pp x I oQ, the we have I oQ >= SR * C L /(2K pp ) Also, If the second stage have over drive voltage V EB2, Vo1 must be able to swing (rt(K pp )-1)*V EB2 above and below V o1Q. Vo1Q must be stabilized by common mode feedback, so that the desired quiescent current in the second stage is achieved.