1. Computer Architecture and Organization Unit -1

2. Digital Logic Circuits – Logic Gates – Boolean Algebra – Map Simplification – Combinational Circuits – Flip-Flops – Sequential Circuits

3. Logic Gates Digital Computers - Imply that the computer deals with digital information - Digital information: is represented by binary digits (0 and 1) Functions of gates can be described by : - Truth Table - Boolean Function - Karnaugh Map

4. GATES Gates – blocks of HW that produce 1 or 0 when input logic requirements are satisfied Gate GATE Binary digital input signal Binary digital output signal

5. Basic Logic Blocks - Combinational Logic Block : logic blocks whose output logic value depends only on the input logic values - Sequential Logic Block : logic blocks whose output logic value depends on the input values and the state of the blocks

6. Combinational Gates

7. BOOLEAN ALGEBRA Boolean Algebra * Algebra with Binary(Boolean) Variable and Logic Operations * Boolean Algebra is useful in Analysis and Synthesis of Digital Logic Circuits - Input and Output signals can be represented by Boolean Variables, and - Function of the Digital Logic Circuits can be represented by Logic Operations, i.e., Boolean Function(s) - From a Boolean function, a logic diagram can be constructed using AND, OR, and I Truth Table * The most elementary specification of the function of a Digital Logic Circuit is the Truth Table - Table that describes the Output Values for all the combinations of the Input Values, called MINTERMS - n input variables → 2n minterms

8. Logic circuit design

9. Equivalent Circuits

10. Combinational Circuits - Multiplexer - Encoder - Decoder - Adders

11. MULTIPLEXER Combinational Logic Circuits 4-to-1 Multiplexer I0I0 I1I1 I2I2 I3I3 S0S0 S1S1 Y 0 0 I 0 0 1 I 1 1 0 I 2 1 1 I 3 Select Output S 1 S 0 Y

12. ADDERS Half Adder Combinational Logic Circuits x y x y c = xy s = xy’ + x’y = x  y xyxy cscs 0 0 0 1 1 0 0 1 1 1 1 0 x y c s 0 1 0 0 0 0 1 1

13. Full Adder 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 c n = xy + xc n-1 + yc n-1 = xy + (x  y)c n-1 s = x’y’c n-1 +x’yc’ n-1 +xy’c’ n-1 +xyc n-1 = x  y  c n-1 = (x  y)  c n-1 x y c n-1 x y cncn s xyxy ScnScn Full Adder x y c n-1 c n s 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 0

14. Encoder

15. NAND gate decoder

16. Sequential Logic Blocks Flip – Flop Latch Latch Vs. Flip –Flop Counters Registers

17. Flip Flops

18. D Flip Flop

19. Latch A latch is a kind of bistable multivibrator, an electronic circuit which has two stable states and thereby can store one bit of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably.

20. S - R Latch The symbol for an SR latch. SR latch operation SRAction 00Keep state 01Q = 0 10Q = 1 11 Restricted combination

21. D-LATCH D-Latch Forbidden input values are forced not to occur by using an inverter between the inputs Flip Flops Q Q’ D(data) E (enable) D Q E Q’ D Q D Q(t+1) 0 1

22. Latch vs. Flip Flop Latch is a edge triggered device whereas Flip flop is a level triggered. Latches are faster and flip flops are slower. Latches take less power to implement than flip- flops. The output of a latch changes independent of a clock signal whereas the Output of a Flip - Flop changes at specific times determined by a clocking signal. In Latch We do not require clock pulses and flip flops are clocked devices.

23. EDGE-TRIGGERED FLIP FLOPS Characteristics - State transition occurs at the rising edge or falling edge of the clock pulse Latches Edge-triggered Flip Flops (positive) respond to the input only during these periods respond to the input only at this time Flip Flops

24. Registers Sequential Circuits D Q C D Q C D Q C D Q C A0A0 A1A1 A2A2 A3A3 Clock I0I0 I1I1 I2I2 I3I3 Shift Registers D Q C D Q C D Q C D Q C Serial Input Clock Serial Output

25. Sequential Circuits - Registers

26. Bidirectional Shift Register with Parallel Load D Q C D Q C D Q C D Q C A0A0 A1A1 A2A2 A3A3 4 x 1 MUX 4 x 1 MUX 4 x 1 MUX 4 x 1 MUX ClockS0S1S0S1 SeriaI Input I0I0 I1I1 I2I2 I3I3 Serial Input

27. Sequential Circuits - Counters

28. Ring counter

29. Johnson Counter