1. RGB to YUV(CDFG) 林鼎原 Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C 2012.3.23 1

2. void main(void) { int a, b, c; ……. RGB_2_Y(I_Frame, O_Frame); ……. } void RGB_2_Y(I_Frame, O_Frame); { int y; for (i=1, i<64, i++) { y=0.257*a +0.504*b+0.098*c+16; write(y) to O_Frame;} } 2

3. Simple Operation description 3

4. CDFG < Mux size i ++ 1 Control line ** * 0.257 0.504 0.098 + + 16v1 + v2 v4 v5 ← y O_P() a bc ←← ← I_P() v3 4

5. Simple Operation description(resource) 5

6. Resource constrained I_P() ← ← * a b 0.257 0.504 ← + v1 v2 0.098 c v3 + v4 v5 ← y O_P() s2 s3 s4 s5 s6 + 16 * * Mux i Control line s7 s8 s1 ++ >= 64 1 system Mux *1 Comparator *1 adder *1 multiplexer *1 multiplexer *2 multiplexer *2, Adder*1 multiplexer *1, Adder*1 Adder*1 資源限制下 ( 每單位時間 2 乘 1 加 ) 需花費 8 個 cycle 完成。 6

7. Time –Constrained Scheduling I_P() ← ← * a b 0.257 0.504 ← + v1 v2 0.098 c v3 + v4 v5 ← y O_P() s2 s3 s4 s5 s6 16 * * Mux i s7 s1 ++ >= 64 1 system Mux *1 Comparator *1 adder *1 multiplexer *3 Adder*2 Adder*1 時間限制在 7 個 cycle 內做完， 代價是需多增加一個乘法器 ( 三個 ) 。 + 7

8. Pipelining Scheduling for 3 Pipeline Latency I_P() ← * a b 0.257 0.504 0.098 ← y O_P() 16 + + I_P() ←← * + * ← * a b 0.504 0.098 ← y O_P() 16 + + I_P() ← ← * + * 0.257 I_P() ← * a b 0.504 0.098 ← y O_P() 16 + + ← ← * + * 0.257 I_P() s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 沒 pipeline 時，相同指令做三次總共需 8*3=24 個 cycle 而有 pipeline(3 個 Latency) ，總共花費 8+(3-1)*3=14 個 cycle ， 節省了 4 個 cycle 。 i ++ 1 s12 s13 s14 >= Mux 64 c c c V1 V4 V2 V5 V3 V1 V2 V4 V5 V3 V1 V4 V2 V5 V3 8

9. Loop Body of 3 Pipeline Latency Loop Body of 3 Pipeline Latency * s1 s2 s3 * * V1 + V3 V2 0.257 0.504 0.098 a b c + + V2 V3 V4 * V5 V6 y 2 2 2 2 Reg 數目 c1 c2 c3 c4 c5 c6 2 registers 1 adders 2 multipliers 16 9

10. Lifetimes of Values 123 V1 V2 V3 V4 V5 V6 123 V1 V3 V5 V2 V4 V6 R1 R2 Left edge algorithm to allocate values into registers 10

11. Lifetimes of Operations 123 C1 C2 C3 C4 C5 C6 * * + * + + 123 C1 C4 C2 C5 C6 C3 * * * + + + 11

12. IP Data Path Generation * 1 23 a bc 0.257 0.504 0.098 1 23 + 1 2 3 16 1 23 R2 R1 M1 M2 M3 M4 R 1 = {V 1, V 3, V 5 } R 2 = {V 2, V 4, V 6 } 12

13. Data Path Optimization * 1 23 a bc 0.257 0.504 0.098 1 23 + 1, 2 3 16 R2 R1 M1 M2 M3 1, 2, 3 R 1 = {V 1, V 3, V 5 } R 2 = {V 2, V 4, V 6 } 13

14. IP Controller Design enableM1M2M3 StateR1R2s1s0s1s0s 11100000 21101010 31110101 R1.ena = R2.ena = State1 + State2 + State3 M1.s1 = M2.s1 = M3.s = State3 M1.s0 = M2.s0 = State2 S1S2S3S0 reset S0: reset S1: 接收 input data a ，並運算 a*0.257, V2+V3 S2: 接收 input data b ，並運算 b*0.504, V4+V5 S3: 接收 input data c ，並運算 c*0.098, V1+16 ， 每次做完 counter 都會累加 1 ，若 counter<64 ，則回到 S1 重複做。 14

15. Simple Controller Mux Program counter Microcode ROM Microcode ROM INCR Control lines Mode Registers …. Control lines Jump address Control signals from data path or ROM 累加器 計數器 15