1. Fuw-Yi Yang1 數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經 察政章 (Chapter 58) 伏 者潛藏也 道紀章 (Chapter 14) 道無形象, 視之不可見者曰 夷

2. Fuw-Yi Yang2 Text Book: Digital Design 5th Ed. Chap 4 Combinational Logic 4.1 Introduction 4.2 Combinational Circuits 4.3 Analysis Procedure 4.4 Design Procedure 4.5 Binary Adder-Subtractor 4.6 Decimal Adder 4.7 Binary Multiplier 4.8 Magnitude Comparator 4.9 Decoders 4.10 Encoders 4.11 Multiplexers 4.12 HDL Models of Combinational Circuits

3. Fuw-Yi Yang3 Text Book: Digital Design 5th Ed. Chap 4.1 Introduction Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. A combinational circuit performs an operation that can be specified logically by a set of Boolean functions.

4. Fuw-Yi Yang4 Text Book: Digital Design 5th Ed. Chap 4.1 Introduction In contrast, sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of the inputs and the state of storage elements. Because the state of the storage elements is a function of previous inputs, the outputs of a sequential circuit depend not only on present value of inputs, but also on past inputs, and the circuit behavior must be specified by a time sequence of inputs and internal states.

5. Fuw-Yi Yang5 Text Book: Digital Design 5th Ed. Chap 4.2 Combinational Circuits A combinational circuit consists of input variables, logic gates, and output variables. See next page We’ll address three tasks (1) Analyze the behavior of a given logic circuit, (2) Synthesize a circuit that will have a given behavior, and (3) Write HDL models for some common circuits.

6. Fuw-Yi Yang6 Text Book: Digital Design 5th Ed. Chap 4.2 Combinational Circuits

7. Fuw-Yi Yang7 Text Book: Digital Design 5th Ed. Chap 4.3 Analysis Procedure The first step in the analysis is to make sure that the given circuit is combinational and not sequential. The diagram of a combinational circuit has logic gates with no feedback paths or memory elements. Example see next page

8. Fuw-Yi Yang8 Text Book: Digital Design 4th Ed. Chap 4.3 Analysis Procedure F 2 = AB + AC + BC T 1 = A + B + C T 2 = ABC 1st T 3 = F 2 T 1 F 1 = T 2 + T 3 2nd F 1 = T 2 + T 3 3rd = ABC + F 2 T 1 = ABC + …

9. Fuw-Yi Yang9 Text Book: Digital Design 5th Ed. Chap 4.3 Analysis Procedure

10. Fuw-Yi Yang10 Text Book: Digital Design 5th Ed. Chap 4.4 Design Procedure The design of combinational circuits starts from the specification of the design objective and culminates in a logic circuit diagram or a set of Boolean function from which the logic diagram can be obtained. The procedure involves the following steps: 1. Determine the required number of inputs and outputs 2. Derive the truth table 3. Obtain the simplified Boolean functions 4. Draw the logic diagram

11. Fuw-Yi Yang11 Text Book: Digital Design 5th Ed. Chap 4.4 Design Procedure – Code Conversion Example

12. Fuw-Yi Yang12 Text Book: Digital Design 5th Ed. Chap 4.4 Design Procedure – Code Conversion Example w CDCDCDCD CD ABAB ABAB 111 AB xxxx 11xx w = A + BC + BD x CDCDCDCD CD ABAB 111 ABAB 11 AB xxxx 1xx x = BC + BD+ BD

13. Fuw-Yi Yang13 Text Book: Digital Design 5th Ed. Chap 4.4 Design Procedure – Code Conversion Example w CDCDCDCD CD ABAB 11 ABAB 11 AB xxxx 1xx y = CD + CD z CDCDCDCD CD ABAB 11 ABAB 11 AB xxxx 1xx z = D

14. Fuw-Yi Yang14 Text Book: Digital Design 4th Ed. Chap 4.4 Design Procedure – Code Conversion Example

15. Fuw-Yi Yang15 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Half Adder

16. Fuw-Yi Yang16 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Half Adder c y y x x1 s y y x 1 x1

17. Fuw-Yi Yang17 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Full Adder

18. Fuw-Yi Yang18 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Full Adder c yzyzyzyz yz x 1 x111 s yzyzyzyz x 11 x11

19. Fuw-Yi Yang19 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Full Adder — Implement with 2 Half adder and 1 OR

20. Fuw-Yi Yang20 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Binary Adder A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. The diagram in the next page shows the interconnection of four full-adder circuits to provide a four-bit binary ripple carry adder. The augend's bits of A and the addend bits B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bit.

21. Fuw-Yi Yang21 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Binary Adder

22. Fuw-Yi Yang22 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Binary Adder To demonstrate with a specific example, consider the two binary numbers A = 1011 and B = 0011. Their sum S = 1100 is formed with the four-bit adder as follows: Subscript i:3 2 1 0 Input carry Augend Addend Sum Output carry 0 1 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 C i A i B i S i C i+1

23. Fuw-Yi Yang23 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation The addition of two binary numbers in parallel implies that all the bits of the augend and addend are available for computation at the same time. As in any combinational circuit, the signal must propagate through the gates before the correct output sum is available in the output terminals. The total propagation time is equal to the propagation delay of a typical gate, times the number of gate levels in the circuit. The longest propagation delay time in an adder is the time it takes the carry to propagate through the full adder.

24. Fuw-Yi Yang24 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation The signal from the input carry C i to the output carry C i+1 propagates through an AND gate and an OR gate, which constitute two gate levels. If there are four full adder, the output carry C 4 would have 2 * 4 = 8 gate level from C 0 to C 4. For an n-bit adder, there are 2n gate levels for the carry to propagate from input to output.

25. Fuw-Yi Yang25 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation Direct implementation to reduce propagation delay: Input: C 0, A 0, A 1, A 2, A 3, B 0, B 1, B 2, B 3, Output: C 1, C 2, C 3, C 4, S 0, S 1, S 2, S 3 S 0 = A 0  B 0  C 0, (cost 18, 4 gates delay( 兩次 , 每次  2 gates delay)) C 1 = A 0 B 0 + A 0 C 0 + B 0 C 0 (cost 13, 2 gates delay (Two-level 實作 ))

26. Fuw-Yi Yang26 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation S 1 = A 1  B 1  C 1 (cost 18, 6 gates delay( 兩次 , 每次  2 gates delay), C 1 2 gates delay) C 2 = A 1 B 1 + A 1 C 1 + B 1 C 1 = A 1 B 1 + A 1 A 0 B 0 + A 0 B 1 B 0 + A 1 A 0 C 0 + A 1 B 0 C 0 + A 0 B 1 C 0 + B 1 B 0 C 0 (cost 35, 2 gates delay (Two-level 實作 ))

27. Fuw-Yi Yang27 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation S 2 = A 2  B 2  C 2 (cost 18, 6 gates delay( 兩次 , 每次  2 gates delay), C 2 2 gates delay) C 3 = A 2 B 2 + A 2 C 2 + B 2 C 2 = A 2 B 2 + A 2 A 1 B 1 + A 2 A 1 A 0 B 0 + A 2 A 0 B 1 B 0 + A 2 A 1 A 0 C 0 + A 2 A 1 B 0 C 0 + A 2 A 0 B 1 C 0 + A 2 B 1 B 0 C 0 +A 1 B 2 B 1 + A 1 A 0 B 2 B 0 + A 0 B 2 B 1 B 0 + A 1 A 0 B 2 C 0 + A 1 B 2 B 0 C 0 + A 0 B 2 B 1 C 0 + B 2 B 1 B 0 C 0 (cost 87, 2 gates delay (Two-level 實作 ))

28. Fuw-Yi Yang28 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation S 3 = A 3  B 3  C 3 (cost 18, 6 gates delay) C 4 = A 3 B 3 + A 3 C 3 + B 3 C 3 = A 3 B 3 + A 3 A 2 B 2 + A 3 A 2 A 1 B 1 +A 3 A 2 A 1 A 0 B 0 +A 3 A 2 A 0 B 1 B 0 + A 3 A 2 A 1 A 0 C 0 +A 3 A 2 A 1 B 0 C 0 + A 3 A 2 A 0 B 1 C 0 +A 3 A 2 B 1 B 0 C 0 + A 3 A 1 B 2 B 1 + A 3 A 1 A 0 B 2 B 0 + A 3 A 0 B 2 B 1 B 0 + A 3 A 1 A 0 B 2 C 0 + A 3 A 1 B 2 B 0 C 0 + A 3 A 0 B 2 B 1 C 0 + A 3 B 2 B 1 B 0 C 0 + A 2 B 3 B 2 + A 2 A 1 B 3 B 1 + A 2 A 1 A 0 B 3 B 0 + A 2 A 0 B 3 B 1 B 0 + A 2 A 1 A 0 B 3 C 0 + A 2 A 1 B 3 B 0 C 0 + A 2 A 0 B 3 B 1 C 0 + A 2 B 3 B 1 B 0 C 0 +A 1 B 3 B 2 B 1 + A 1 A 0 B 3 B 2 B 0 + A 0 B 3 B 2 B 1 B 0 +A 1 A 0 B 3 B 2 C 0 +A 1 B 3 B 2 B 0 C 0 + A 0 B 3 B 2 B 1 C 0 + B 3 B 2 B 1 B 0 C 0 (cost 207, 2 gates delay )

29. Fuw-Yi Yang29 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation Generate carries: Total Cost = 13 + 35 + 87 + 207 = 342 Propagation delay: 2 gates delay Generate sums: Total Cost = 18 + 18 + 18 + 18 = 72 Propagation delay: 6 gates delay S 0 = A 0  B 0  C 0, Cost = 18 S 1 = A 1  B 1  C 1, Cost = 18 S 2 = A 2  B 2  C 2, Cost = 18 S 3 = A 3  B 3  C 3, Cost = 18

30. Fuw-Yi Yang30 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation There are several techniques for reducing the carry propagation time in parallel adder. The most widely used technique employs the principle of carry lookahead logic. Let P i = A i  B i, G i = A i B i. Then S i = P i  C i, C i+1 = G i +P i C i. G i is called a carry generate; P i is called a carry propagate. C 0 = input carry, C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 C 0

31. Fuw-Yi Yang31 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation P i = A i  B i, G i = A i B i, C 0 = input carry, C 1 = G 0 + P 0 C 0, (Cost 6 + 3 (G 0 )) C 2 = G 1 + P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0, (Cost 12 + 3 (G 1 )) C 3 = G 2 + P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 C 0, (Cost 18 + 3 (G 2 ))) C 4 = G 3 + P 3 C 3 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0. (Cost 25 + 3 (G 3 ))) Exor (P i ) implemented in 2-levels,AND (G i ) implemented in 1-level. C i can be implemented within 4 = (max(2, 1) + 2) gates delay.

32. Fuw-Yi Yang32 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation Generate carries: Total Cost = 6+3 + 12+3 + 18+3 + 25+3 = 73 Propagation delay: 4 gates delay Generate sums: Total Cost = 18 + 18 + 18 + 18 = 72 Propagation delay: 6 P i = A i  B i, S i = P i  C i, Cost 18, delay 4 gates S 0 = A 0  B 0  C 0, Cost = 18 S 1 = A 1  B 1  C 1, Cost = 18 S 2 = A 2  B 2  C 2, Cost = 18 S 3 = A 3  B 3  C 3, Cost = 18

33. Fuw-Yi Yang33 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation Since the Boolean function for each output carry is expressed in sum-of-product form, each function can be implemented with one level of AND gates followed by an OR gate. Next pages shows the implementation of carry lookahead generators, C 1, C 2, and C 3. (C 4 not shown) Also, a four-bit adder with carry lookahead is shown.

34. Fuw-Yi Yang34 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Carry Propagation

35. Fuw-Yi Yang35 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Binary Adder 2 gates delay

36. Fuw-Yi Yang36 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Ripple carry, Direct, Carry look ahead Ripple Carry Direct implementation Carry look ahead Generate carry Cost: 52 Delay: 2*n Cost: 342 Delay:2 Cost: 73 Delay: 4 Generate sum Cost: 84 Delay: 2*n O(n) Cost: 72 Delay:6 O(0) Cost: 72 Delay: 6 O(0)

37. Fuw-Yi Yang37 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Binary Subtractor The subtraction of unsigned binary numbers can be done most conveniently by means of complements, as discussed in Section 1.5. Remember that the subtraction A - B can be done by taking the 2’s complement of B and adding it to A. The 2’s complement can be obtained by taking the 1’s complement and adding 1 to the least significant pair of bits. The 1’s complement can be implemented with inverters, and a 1 can be added to the sum through the input carry. Next page shows a four-bit adder-subtractor.

38. Fuw-Yi Yang38 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Binary Adder

39. Fuw-Yi Yang39 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Overflow When two numbers with n digit each are added and the sum is a number occupying n + 1 digits, we say that an overflow occurred. When two unsigned numbers are added, an overflow is detected from the end carry out of the most significant position. In the case of signed numbers are added, two details are important: the leftmost bit always represents the sign, and negative number are in 2’s complement form.

40. Fuw-Yi Yang40 Text Book: Digital Design 5th Ed. Chap 4.5 Binary Adder-Subtractor Overflow An overflow cannot occur after an addition if one number is positive and the other is negative. An overflow may occur if the two numbers added are both positive or both negative. An overflow condition can be detected by observing the carry into the sign bit position and the carry out of the sign bit position. See the output variable V = C 3  C 4 in the previous diagram for four-bit adder-subtractor.

41. Fuw-Yi Yang41 Text Book: Digital Design 5th Ed. Chap 4.6 Decimal Adder BCD adder Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in binary and produce a result that ranges from 0 through 19 (9 + 9 + 1 carry). These binary numbers are listed in the next page.

42. Fuw-Yi Yang42 Text Book: Digital Design 4th Ed. Chap 4.5 Binary Adder-Subtractor Binary Adder

43. Fuw-Yi Yang43 Text Book: Digital Design 4th Ed. Chap 4.6 Decimal Adder BCD adder From truth table, output carry C = K + Z 8 Z 4 + Z 8 Z 2. When carry occurs, the addition of 0110 to the binary sum converts it to the correct BCD representation.

44. Fuw-Yi Yang44 Text Book: Digital Design 5th Ed. Chap 4.7 Binary Multiplier two-bit by two-bit binary multiplier Multiplicand Multiplier

45. Fuw-Yi Yang45 Text Book: Digital Design 5th Ed. Chap 4.7 Binary Multiplier four-bit by three-bit binary multiplier Multiplicand B 3 B 2 B 1 B 0 Multiplier  A 2 A 1 A 0 Adder 1 A 0 B 3 A 0 B 2 A 0 B 1 A 0 B 0 A 1 B 3 A 1 B 2 A 1 B 1 A 1 B 0 Adder 2 A 2 B 3 A 2 B 2 A 2 B 1 A 2 B 0 The result will be (4 + 3) bits, we need (4 * 3) AND gates and two four-bit adders to produce a product of seven bits. The logic diagram is shown in next page.

46. Fuw-Yi Yang46 four-bit by three-bit binary Multiplier B 3 B 2 B 1 B 0  A 2 A 1 A 0

47. Fuw-Yi Yang47 Text Book: Digital Design 5th Ed. Chap 4.8 Magnitude Comparator four-bit magnitude comparator A = A 3 A 2 A 1 A 0 B = B 3 B 2 B 1 B 0 Let x i = (A i  B i )' = A i B i + A i ' B i ' for i = 0, 1, 2, 3. (A = B) = x 3 x 2 x 1 x 0 (A > B) = A 3 B 3 ' + x 3 A 2 B 2 ' + x 3 x 2 A 1 B 1 ' + x 3 x 2 x 1 A 0 B 0 ' (A < B) = A 3 'B 3 + x 3 A 2 'B 2 + x 3 x 2 A 1 'B 1 + x 3 x 2 x 1 A 0 'B 0 The logic diagram is shown in next page.

48. Fuw-Yi Yang48 Text Book: Digital Design 4th Ed. Chap 4.8 Magnitude Comparator four-bit magnitude comparator four-bit comparator

49. Fuw-Yi Yang49 Text Book: Digital Design 5th Ed. Chap 4.9 Decoders three-to-eight-line decoder The logic diagram is shown in next page.

50. Fuw-Yi Yang50 Text Book: Digital Design 4th Ed. Chap 4.9 Decoders three-to-eight-line decoder

51. Fuw-Yi Yang51 Text Book: Digital Design 5th Ed. Chap 4.9 Decoders two-to-four-line decoder with enable input 0

52. Fuw-Yi Yang52 Text Book: Digital Design 5th Ed. Chap 4.9 Decoders 4  16 decoder constructed with two 3  8 decoder Please construct a 3  8 decoder with enable Input. Hint: using Fig 4.18.

53. Fuw-Yi Yang53 Text Book: Digital Design 5th Ed. Chap 4.9 Decoders Combinational logic implementation Implementation of a full adder with a 3  8 decoder. S =  (1, 2, 4, 7) C =  (3, 5, 6, 7)

54. Fuw-Yi Yang54 Text Book: Digital Design 5th Ed. Chap 4.10 Encoders Octal-to-Binary Encoder The encoder defined above has the limitation that only one input can be active at any given time.

55. Fuw-Yi Yang55 Text Book: Digital Design 5th Ed. Chap 4.10 Encoders Four-input Priority Encoder Output variable V indicates whether a valid input occurs. It can be seen that the input variable D 3 is with the highest priority. Next page shows the logic diagram.

56. Fuw-Yi Yang56 Text Book: Digital Design 4th Ed. Chap 4.10 Encoders Priority Encoder V D2D3D2D3 D2D3D2D3 D2D3D2D3 D2D3D2D3 D0D1D0D1 111 D0D1D0D1 1111 D0D1D0D1 1111 D0D1D0D1 1111 V = D 0 + D 1 + D 2 + D 3 x = ? y = ?

57. Fuw-Yi Yang57 Text Book: Digital Design 5th Ed. Chap 4.10 Encoders Four-input Priority Encoder

58. Fuw-Yi Yang58 Text Book: Digital Design 5th Ed. Chap 4.11 Multiplexers Two-to-one-line multiplexer

59. Fuw-Yi Yang59 Text Book: Digital Design 5th Ed. Chap 4.11 Multiplexers Four-to-one-line multiplexer

60. Fuw-Yi Yang60 Text Book: Digital Design 4th Ed. Chap 4.11 Multiplexers Quadruple Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection logic. Quadruple 2-to-1-line multiplexer (select 4 bits)

61. Fuw-Yi Yang61 Text Book: Digital Design 5th Ed. Chap 4.11 Multiplexers Boolean Function Implementation

62. Fuw-Yi Yang62 Text Book: Digital Design 4th Ed. Chap 4.11 Multiplexers Boolean Function Implementation

63. Fuw-Yi Yang63 Text Book: Digital Design 5th Ed. Chap 4.11 Multiplexers Three-State Gates

64. Fuw-Yi Yang64 Text Book: Digital Design 5th Ed. Chap 4.11 Multiplexers Multiplexers with three-state gates

65. Fuw-Yi Yang65 Text Book: Digital Design 5th Ed. Chap 4.12 HDL Models of Combinational Circuits HDL Example 4.1 module Decoder 2  4(D, A, B, enable); output [0: 3] D; input A, B; input enable; wire A_not, B_not, enable_not; not G1(A_not, A); G2(B_not, B); G3(enable_not, enable); nand G4(D[0], A_not, B_not, enable-not); G5(D[1], A_not, B, enable-not); G6(D[2], A, B_not, enable-not); G7(D[3], A, B, enable-not); endmodule