1. FPGA firmware of DC5 FEE

2. Outline

3. List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)

4. Module Connection Signal and Clock rate — Optical Tx and Rx3.1104 Gbps — Master CLK38.88 MHz (was 155.52MHz) — Command 38.88 Mbps (was 155.52MHz) — FLT (First level Trigger) Pulse sync to 38.88MHz CLK — Data155.52 Mbps Command & FLT GANDALFDCMFEM Optical fiber Ethernet cable Master CLK Data FEM …… Optical Tx Optical Rx x1 x8 x20 Totally 1 GANDALF 8 DCM 160 FEM

5. Clock Structure GANDALF DCM FEM Optical Tx Optical Rx Xilinx Transceiver OSC 155.52M Rx clock 155.52M command Deformater PLL1 PLL2 155.52M FEM Ctrl Logic 77.76M FEM2DCM transmit 155.52MB TDC Clock 38.88M 233.28M 233.28M 90° 2M CMAD setting Deformater is a VHDL code from T. Grussenmeyer. —Master 38.88MHz CLK is generated and phase adjusted by RX CLK and command from GANDALF. Two TDC CLKs will be 233.28MHz = 38.88MHz x 6. (248MHz now) 155.52MB is a phase adjustable CLK for data output.

6. First Level Trigger In DCM, First level trigger is generated according to a specific command/data pattern from GANDALF. A FLT pulse is distributed to FEMs sync to master CLK. GANDALF Optical Tx Optical Rx Xilinx Transceiver Rx clock 155.52M command Deformater Clock 38.88M FLT(first level trigger)

7. TCS Reset signal TCS reset will be distributed to FEMs by a dedicated command sync to master CLK. – Not fully implemented yet. A comment to FEMs to reset TDC counters in the current implemetation. – Need inputs about TCS Reset command/pattern from GANDALF.

8. Trig Time FEM TDC Block Diagram CMAD x16 inputs TDC x16 FLT trigger TDC x1 Trigger Logic Flag Reset Trigger Match Trig Flag Event FIFO (512 x 32bit) DCM & FEM (8b/10b) Link logic Buffer Ctrl Logic x16 Time x16 Flag x16 Reset Cycling buffer (512 hits) Trig Flag Write point # of TDC hits 0100110110 Serial data Command handler It will be 4096x32 bit. Trig Time Data

9. TDC counter TDC value for each hit is 16 bit. – MSB 14 bit is from a counter by 233MHz CLK. – LSB 2 bit is determined by a four bit pattern latched with 233MHz CLK and 233MHz 90 o CLK. 14 bits2 bits 233.28M 233.28M 90° 14 bits ≈ 70.3us

10. Trigger Match Time resolution – TDC time = 16 bit (1ns lsb) – Trigger Latency = 12 bit (4ns lsb) – Matching Window = 12 bit (4ns lsb) (T trig –T latency –T window ) < T hit < (T trig –T latency +T window ) Matching process stops at – 16 matched hits. – No more TDC hit left (Max hits for matching process is 255). – 4 unmatched hits after last matched hit. – All conditions will be adjusted according to the final noise level.

11. DCM block diagram 010011 Serial data DCM & FEM (8b/10b) Transmitter x20 DCM to FEM Command FIFO x20 FEM to DCM Data FIFO (512 x 32bit) x20 Command handler GANDALF DCM Link logic Transceiver 010011 Serial data TCS info command FLT(first level trigger) FEM to DCM Frame flag FIFO x20 data packing data DCM & FEM (8b/10b) Receiver x20 010011 Serial data

12. DCM pack FEM data procedure Idle Any FEM frame valid No Wait 4 system clock Yes Timeout or all FEM valid No Send S-link begin mark Yes Send S-link header Scan all FEM FIFO frame valid Readout FEM data EOF word No All FIFO scan over Yes No Send S-link end mark Yes Power on reset No

13. Data Loss issue (DCM to GANDALF) Previous version of DCM FPGA design, the same state machine controls both command flow and data flow. – When a command arrives in DCM, the data packing and transmission will be interrupted and caused the data loss. The latest DCM FPGA design is modified to have independent control for: – Command flow (GANDALF  DCM  FEMs) – Data flow (FEMs  DCM  GANDALF)

14. Latest Data transmission Test (with new DCM firmware) 2. DCM generates 100k trigger in one sec. GANDALFDCMFEM 5. Use counter check valid data frame number from FEM Optical fibre x1 Count mode USB Ethernet cable 1. Pass command Trigger_on to DCM 3. FEM send 1 data frame to DCM per trigger 4. Packing data frame and pass to GANDALF 6. Pass data frame to PC7. Save data into file and use program analysis Test result – DCM did received 100k data frames from FEM. – The data stored in PC lost about 1.5% data frame.

15. Command Error issue (DCM to FEM) A timing issue, long operational logic path due to – 8b/10b encoding – Multiplexing of commands and fill pattern The latest DCM FPGA design add pipeline/FIFO to reduce logic path – Under test

16. Command lost issue (PC with USB connection to GANDALF) When PC is taking data from GANDALF and sending commands to GANDALF at the same time, – DCM receives commands with error or loses commands. Try to stop trigger first before sending commands.

17. Summary

19. Backup

20. Command lost (DCM to FEM) DCM to FEM Command FIFO Timing issue when do 8b10b encoder – Original structure 8b10b encoder control command Idle(K28.5)Trig func Mode control status 0101001100 ERROR control Controller + Serializer

21. Fix Command lost (DCM to FEM) New version DCM to FEM CMD FIFO CMD CMD / idle Selector 32b to 8b FIFO 8b10b encoder Serializer Trig mode func Mode select with command for DCM 0101001100 FLT pulse signal