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2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

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Presentation on theme: "2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2."— Presentation transcript:

1 2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2

2 Equality Detector XNOR X Y Z Z = ~(X ^ Y) X Y Z 0 0 1 0 1 0 1 0 0 1 1 1

3 Z = 1 if A=B=C

4 NASA Tech Briefs November 2001 X0 X1 X2 X3 X4 X5 c0 c1 Y0 Y1 Y2 Y3 A B X = 111111 Y = 1111 X = 000101 Y = 0101 X = 011101 Y = 0111 X = 110101 Y = 1000

5 -- Title : sat4bit -- Author : haskell --------------------------------------------------------- -- Description : Lab2a --------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; entity sat4bit is port( x : in STD_LOGIC_VECTOR(5 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end sat4bit; x0 x1 x2 x3 x4 x5 y0 y1 y2 y3 A B c0 c1

6 architecture sat4bit of sat4bit is signal c0,c1,s: STD_LOGIC; signal A,B:STD_LOGIC_VECTOR(3 downto 0); signal sel: STD_LOGIC_VECTOR(3 downto 0); begin A(3) <= x(5); A(2 downto 0) <= not x(5) & not x(5) & not x(5); B <= x(3 downto 0); c1 <= x(3) xnor x(4); c0 <= x(4) xnor x(5); s <= c0 and c1; sel <= s & s & s & s; y <= (not sel and a) or (sel and b); end sat4bit; x0 x1 x2 x3 x4 x5 c0 c1 y0 y1 y2 y3 A B

7 The circuit will take a 6-bit two’s complement number with a signed value between –32 and +31 and convert it to a 4-bit two’s complement number with a signed value between –8 and +7. Negative input values less than –8 will be saturated at –8. Positive input values greater than +7 will be saturated at +7. Note the behavior of the circuit Make a truth table to see what the output looks like

8 xy 000000x(3 downto 0) ------x(3 downto 0) ------x(3 downto 0) 000111x(3 downto 0) 0010000111 ------0111 ------0111 0111110111 1000001000 ------1000 ------1000 1110001000 111001x(3 downto 0) ------x(3 downto 0) ------x(3 downto 0) 111111x(3 downto 0) Truth Table for 2’s Complement 4-Bit Saturator

9 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity mysat4bit is port( x : in STD_LOGIC_VECTOR(5 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end mysat4bit; architecture mysat4bit of mysat4bit is begin process(x) begin if x <= "000111" then y <= x(3 downto 0); elsif x <= "011111" then y <= "0111"; elsif x <= "111000"then y <= "1000"; else y <= x(3 downto 0); end if; end process; end mysat4bit; Note: must include this file to use relational operator <= xy 000000x(3 downto 0) ------x(3 downto 0) ------x(3 downto 0) 000111x(3 downto 0) 0010000111 ------0111 ------0111 0111110111 1000001000 ------1000 ------1000 1110001000 111001x(3 downto 0) ------x(3 downto 0) ------x(3 downto 0) 111111x(3 downto 0)


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