1. 1 Interrupts, Resets Today: First Hour: Interrupts –Section 5.2 of Huang’s Textbook –In-class Activity #1 Second Hour: More Interrupts Section 5.2 of Huang’s Textbook –In-class Activity #2

2. 2 Example Task Read the output of the 4-bit data source every time the push button is pressed, and display the result. 4-bit Data Source Push Button Computer (HC11 chip) Display

3. 3 One Method... 4-bit Data Source Push Button Computer (HC11 chip) Display START BUTTON PRESSED? 1 ms delay BUTTON PRESSED? READ 4-BIT INPUT UPDATE DISPLAY NO YES Why do we have this? Software switch debouncing Why do we have this? Software switch debouncing This style of computer input/output is called Polled I/O because we’re constantly polling the pushbutton This style of computer input/output is called Polled I/O because we’re constantly polling the pushbutton

4. 4 Is Polling Bad? Eats up a lot of CPU cycles doing nothing! –We’re repeatedly checking the button –Each time the button is pressed, we delay by 1 ms by going around in a loop, wasting time –This is also called “busy wait” grab the CPU’s attentionWe could do better if only we could somehow grab the CPU’s attention momentarily whenever the button is pressed! We could do even better if the 1 ms delay could be achieved without a delay loop!

5. 5 Introducing Interrupts A mechanism to interrupt the CPU, i.e., steal it for a little while to service the interrupting device (a button in our example) A mechanism to interrupt the CPU, i.e., steal it for a little while to service the interrupting device (a button in our example)

6. 6 Why are Interrupts Important? They allow multiple processes to run on a computer They allow the CPU to be shared, greatly extending its ability For example, the CPU can be doing something else when “waiting” for the button to be pressed They allow multiple processes to run on a computer They allow the CPU to be shared, greatly extending its ability For example, the CPU can be doing something else when “waiting” for the button to be pressed

7. 7 Interrupt Method START INITIALIZE DO SOMETHING USEFUL useful or otherwise.... 4-bit Data Source Push Button Computer (HC11 chip) Display Suppose that the computer is doing something... DO SOMETHING USEFUL Key Pressed

8. 8 Interrupt Method START INTERRUPT SERVICE ROUTINE READ THE 4-BIT INPUT UPDATE THE DISPLAY RETURN FROM INTERRUPT START INITIALIZE DO SOMETHING USEFUL Key Pressed The CPU is temporarily interrupted. An Interrupt Service Routine is entered The CPU is temporarily interrupted. An Interrupt Service Routine is entered The CPU now resumes where it left off! START INTERRUPT SERVICE ROUTINE READ THE 4-BIT INPUT UPDATE THE DISPLAY RETURN FROM INTERRUPT DO SOMETHING USEFUL

9. 9 Interrupts are Transparent The program that was interrupted does not have a clue that it was interrupted!! Interrupt Service Routines need to leave registers untouched Interrupt Service Routines need to be extremely short and quick WHY?? The program that was interrupted does not have a clue that it was interrupted!! Interrupt Service Routines need to leave registers untouched Interrupt Service Routines need to be extremely short and quick WHY??

10. 10 Interrupts vs. Subroutines Interrupt Service routines may look a bit like subroutines, but they are very different. Subroutines are not transparent. The calling routine is aware of the subroutine call. Interrupt Service Routines are initiated by hardware, with some exceptions (e.g., SWI). The CPU hardware automatically saves and restores all registers. With subroutines, the programmer has to write code for saving and restoring. In general, not all registers are saved.

11. 11 Interrupt Sources Hardware Sources External Pushbuttons Timers Serial Communication Systems... Software Sources SWI instruction Interrupts can come from several sources

12. 12 Interrupt Priority For example, sources requiring a more timely response get higher priority. At 9600 bits/sec, the RS-232 port on your PC produces an interrupt about once every 2000 CPU cycles. The 68HC11 timer produces an interrupt once every 2 16 CPU cycles. The timer has higher priority in this case. Different Sources can have different priorities

13. 13 Do Activity #1 Now

14. 14 What is an interrupt? A special event that requires the CPU to stop normal program execution and perform some service related to the event. E.g.: I/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0 etc. Functions of Interrupts: -Coordinating I/O activities and preventing CPU from being tied up -Providing a graceful way to exit from errors -Reminding the CPU to perform routine tasks Interrupts: Recap

15. 15 Why do we need to use masking and priority to manage interrupts ? Interrupt Maskability: -Interrupts that can be ignored by the CPU are called maskable interrupts. A maskable interrupt must be enabled before it can interrupt the CPU. An interrupt is enabled by setting an enable flag. Interrupts that can’t be ignored by the CPU are called non-maskable interrupts. Interrupt priority: - The order in which the CPU will service interrupts when all of them occur at the same time. Managing Interrupts

16. 16 68HC11 Interrupts SCI serial system SPI serial transfer Pulse accumulator input edge Pulse accumulator overflow Real time interrupt IRQ pin XIRQ pin Timer overflow Timer output compare 5 Timer output compare 4 Timer output compare 3 Timer output compare 2 Timer output compare 1 Timer input capture 3 Timer input capture 2 Timer input capture 1 The 68HC11 supports 16 hardware interrupts and two software interrupts. Hardware Interrupts Software interrupts: SWI instruction, and illegal opcode interrupt. Both are nonmaskable.

17. 17 Who is it?? When an interrupt request is detected by the CPU, it needs a way to find out the source of the interrupt. One approach: Polling Better approach: Vectored interrupts Interrupt Vector: The starting address of the interrupt service routine (ISR), stored in a standard location.

18. 18 Vector addressInterrupt sourcePriority FFC0, C1... FFD4, D5 FFD6, D7 FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF reserved... SCI serial system SPI serial transfer complete pulse accumulator input edge pulse accumulator overflow timer overflow timer output compare 5 timer output compare 4 timer output compare 3 timer output compare 2 timer output compare 1 timer input capture 3 timer input capture 2 timer input capture 1 real timer interrupt IRQ pin interrupt XIRQ pin interrupt SWI illegal opcode trap COP failure COP clock monitor fail RESET lowest highest Eg: 6811 Int. Vector Address & Priority Whenever timer overflows, the CPU executes the ISR starting at address stored here.

19. 19 Interrupt Service Routine (ISR): Piece of code which handles the interrupt Interrupt Vector: Starting address of the interrupt service routine Interrupt Vector Table: A table where all interrupt vectors are stored. Similar to I/O Jump Table Implementing Interrupts ISR Code ISR Address Jump to ISR Interrupt Vector Address

20. 20 Interrupt Service Cycle 1. Saving the program counter value in the stack 2. Saving the CPU status (including the CCR register and some other registers) in the stack 3. Identifying the cause of interrupt 4. Resolving the starting address of the corresponding interrupt service routine through the Interrupt Vector Table 5. Executing the interrupt service routine (ISR) 6. Restoring the CPU status and the program counter from the stack 7. Restarting the interrupted program

21. 21 Do Activity #2 Now Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Huang Textbook, & HC11 PRG Required Reading: – Sec 4.1-4.7 of Huang This reading is necessary for getting points in the Studio Activity!