1. ATS Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM- based FPGAs Keheng Huang, Yu Hu, Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences Gengxin Hua, Hongjin Liu, Bo Liu Beijing Institute of Control Engineering 2011-11-23

2. Purpose Soft error mitigation scheme. SRAM-based FPGAs Utilize logic masking effect During logic synthesis Without additional area overhead

3. Outline Background. Motivation FEC-based soft error mitigation scheme Experimental results Conclusions

4. Outline Background. Motivation FEC-based soft error mitigation scheme Experimental results Conclusions

5. Background Architecture of SRAM-based FPGAs.

6. Background Architecture of SRAM-based FPGAs.

7. Background Architecture of SRAM-based FPGAs.

8. Background Architecture of SRAM-based FPGAs. SRAM bits 97%3%

9. Background Architecture of SRAM-based FPGAs. 70% The reliability of routing resources is of great importance, and needs to be seriously considered SRAM bits 97%3%

10. Background FPGA EDA flow. Design specification Gate-level netlist Bit Stream Synthesis and mapping Placement and routing

11. Background FPGA EDA flow. Design specification Gate-level netlist Bit Stream Synthesis and mapping Placement and routing ROSE [Hu, ICCAD’08], IPR [Feng, ICCAD’09], R2 [Jose, DAC’10] Boolean matching High computational complexity Dual-output resynthesis [Lee, ASP-DAC’10] LUT Dual-output encoding Relies on dual-output feature of FPGAs

12. Outline Background. Motivation FEC-based soft error mitigation scheme Experimental results Conclusions

13. Motivation There are a lot of free LUT entries (all 6 LUT inputs are used%=43.71%), which can be used to mitigate soft errors

14. Outline Background. Motivation FEC-based soft error mitigation scheme Experimental results Conclusions

15. FEC-based soft error mitigation Logic masking effect.

16. FEC-based soft error mitigation Address Hamming Distance. –The Hamming Distance between the addresses of two LUT entries If (H[addr(entry 0, entry 2 )]=H[00,10]=1) && the configuration bits are the same Then, the fault at corresponding inputs will be logic masked

17. FEC-based soft error mitigation Flowchart of the design.

18. FEC-based soft error mitigation Establishing FEC models.

19. FEC-based soft error mitigation Establishing FEC models.

20. FEC-based soft error mitigation Cube-based reliability analysis. –Evaluate the reliability of each LUT input FEC replacement with most reliability improvement –One free LUT input FEC 1.x: –Two free LUT inputs FEC 2: –More than two LUT inputs Combination of FEC 1.x and FEC 2 Keheng Huang, Yu Hu, Xiaowei Li, “Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation,” in Proc. of DATE, 2011. pp.58-63

21. Outline Background. Motivation FEC-based soft error mitigation scheme Experimental results Conclusions

22. Experimental results MCNC benchmark set Synthesis and mapping ： Berkeley ABC mapper Gate-level netlist SRAM bits Architecture of FPGA: 4 6-input LUTs/CLB Virtex like routing Hardware: Xeon 6GB Workstation Software: Java Placement and Routing ： VPR toolset

23. Experimental results Area. –# of LUTs Soft Error Rate (SER) –Cube-based reliability analysis Critical-path delay –Reported by VPR Computational complexity –Runtime

24. Experimental results Area. –# of LUTs –No area overhead

25. SER : reduced by 21.72%. ROSE:25% IPR:49% Dual-output 27% Experimental results resynthesis:

26. Critical-path delay. –Reported by VPR –Increased by 4.25% Experimental results

27. Computational complexity. –Runtime : 28.83ms ROSE:184.2s IPR:5.58s Dual output 6s Experimental results resynthesis:

28. Outline Background. Motivation FEC-based soft error mitigation scheme Experimental results Conclusions

29. FEC-based soft error mitigation. –Mitigate Soft Errors in FPGA Reduce SER by 21% –Small performance overhead Critical-path delay increase: 4.25% –No area overhead (exploiting free LUT entries) –Does not rely on specific FPGA devices Suitable for all LUT based FPGAs

30. Q & A