1. PLC ARCHITECTURE - CPU by
Dr. Amin Danial Asham

2. References
Programmable Controllers- Theory and Implementation, 2nd Edition, L.A. Bryan and E.A. Bryan

3. Basic Architecture of PLC
CPU, which consists of
Input-Output (I/O) Modules, which may attached to the CPU, in the same panel with the CPU, or remote from the CPU.
Processor,
Memory,
and
Power Supply

4. CPU
The CPU contains all of the necessary elements that form the intelligence of the system; processor, memory, and power supply, which are all in a constant interaction.
The processor executes the program stored in the memory system in the form of ladder diagrams.
The power supply feeds the power to the processor and memory components

5. PROCESSOR
PLC’s are powered by modern microprocessors that perform mathematical operations, data handling, and routines that were not possible with relays or the hardwired logic processor.
The Main function of the processor is to control and govern the entire system.
It performs this function by interpreting and executing a collection of system programs known as the executive. The executive, a group of supervisory programs, is permanently stored in the processor and is considered a part of the controller itself.
By executing the executive, the processor can perform all of its control, processing, communication, etc.. The executive performs the communication between the PLC system and the other peripherals such as monitoring field devices; reading diagnostic data from the power supply, I/O modules, and memory; and communicating with an operator interface.
Some PLC’s have multi-processors to perform parallel processing and hence increasing the speed for large programs for large control systems.
Microprocessors used in PLC may have different clock speeds and word sizes (8, 16, 32 bits) which have a direct impact on the speed. For example 32 bit data microprocessor reads twice as much data read in one operation by 16 bit microprocessor.

6. PROCESSOR SCAN
Scan cycle is a repeated operation during which the processor performs the following operations continuously:
Reads the input memory data to be used in the control program (Ladder diagram).
Program scan: Runs the user ladder program and generates the output values.
Writes the outputs to the output memory (Updates outputs) . The internal processor signal, which indicates that the program scan has ended, is called the end-of-scan (EOS) signal.
Repeating the cycle.

7. PROCESSOR SCAN (continue)
The time needed to complete a one full scan cycle is called Scan Time. Therefore, the scan time is the total time the PLC takes to complete the program and I/O update scans.
The program scan time generally depends on two factors:
The amount of memory taken by the control program.
The type of instructions used in the program (which affects the time needed to execute the instructions).
There are other factors that may affect the scan time such as communication with remote I/O’s and communication with a monitoring device because the microprocessor must send data about the status of the coils and contacts.

8. PROCESSOR SCAN (continue)
A processor is able to read an input as long as the input signal is not faster than the scan time. In other words, the input signal does not change state twice during the processor’s scan time —(e.g. ON to OFF to ON or vice versa).
For instance, if a controller has a total scan time of 10 msec must monitor an input signal that changes states twice during an 8 msec period (less than the scan), the programmable controller will not be able to “see” the signal, resulting in a possible machine or process malfunction.

9. PROCESSOR SCAN (continue)
Example: What occurs during the scanning operation of a programmable controller if the signal(s) from an input field device behave as shown
Solution:
The PLC will detect the pulse of signal (a) even though it was shorter than the scan time since the signal was ON during read section of the scan.
The PLC will detect the first pulse but won’t detect the second pulse
Detected
Not-Detected

10. PROCESSOR SCAN (continue)
To deal with pulses shorter than the scan time the following methods were introduced.
Some PLCs provide software instructions that allow the interruption of the continuous program scan to receive an input or to update an output immediately. These immediate instructions are very useful when the PLC must react instantaneously to a critical input or output.

11. Example:
Illustrate how, in one scan, (a) an immediate instruction will respond to an interrupt input and
(b) the same input instruction can update an immediate output field device, like a solenoid.
(a)
(b)
The immediate instruction will interrupt the control program to read the input signal.
Return
It will then evaluate the signal
Resume program execution
Output Updated
Resume program execution

12. PROCESSOR SCAN (continue)
As another solution, is by using a pulse stretcher module, which stretches the signal so that it will last for at least one complete scan. With this type of interface, the user must ensure that the signal does not occur more than once per two scans; otherwise, some pulses will be lost.
If a large number of pulses must be read in a shorter time than the scan time, a high-speed pulse counter input module can be used to read all the pulses and then send the information to the CPU.

13. ERROR CHECKING
Error checking techniques are used to validate the data sorted in the memory or received over a communication link to avoid processing erroneous data.
There are several error checking techniques, Common error- checking techniques include parity and checksum.
Parity
Parity is an indication if the number of 1’s in a word. There are two types of parity:
Even Parity: The number of 1’s are an even number.
Odd Parity: The number of 1’s is an odd number.

14. Parity (continue) ERROR CHECKING (continue)
An extra bit is added to a word as a most significant bit to adjust the number of ones to be even or odd a required by the used technique.
Example:
If a processor is transmitting a 7-bit ASCII code to a peripheral and an odd parity is required.
Therefore the processor will transmit a 8-bit code P
To keep the number of ones odd P=0, therefore the actual transmitted code is
If the 7-bit transmitted code is , hence the processor will transmit a 8-bit code with P=1 to make it odd parity; that is

15. Parity (continue) ERROR CHECKING (continue)
Parity error checking is a single-error detection method. If one bit of data in a word changes, an error will be detected due to the change in the bit pattern.
However, if two bits change value, the number of 1s will be changed back, and an error will not be detected even though there is a mis- transmission.
If the data transmission is from the programmable controller to a peripheral, the parity method must be pre-specified and must be the same for both devices.
In parity check there is an extra bit for every 8-bits, which causes a loss of 12.5% of the available storage capacity.

16. ERROR CHECKING (continue) Checksum
Checksum error detection spots errors in blocks of many words, instead of in individual words as parity does.
An extra word is added to the end of a block of words that reflects the characteristics of the block, which is called block check character (BCC).
There are several methods of checksum computation,
with the three most common being:
Cyclic Redundancy Check (CRC)
Longitudinal Redundancy Check (LRC)
Cyclic Exclusive-OR Checksum (CX-ORC)

17. ERROR CHECKING (continue) Checksum (continue)
Longitudinal Redundancy Check (LRC)
The LRC operation is simply the logical exclusive-OR of the first word with the second word, the result with the third word, and so on. The final exclusive-OR operation is stored at the end of the block as the BCC.
Example: Get LRC for this four 6-bit words block of data.
Solution:

18. ERROR CHECKING (continue) Checksum (continue)
Cyclic Exclusive-OR Checksum (CX-ORC)
The operation starts with a checksum word containing 0s, which is XORed with the first word of the block. This is followed by a left rotation of the bits in the checksum word. The next word in the data block is XORed with the checksum word and then rotated left.
This procedure is repeated until the last word of the block has been logically operated on. The checksum word is then appended to the block to become the BCC.

19. ERROR CHECKING (continue) Checksum (continue)
Cyclic Exclusive-OR Checksum (CX-ORC) (continue)
Example: Get LRC for this four 6-bit words block of data.
Solution:

20. CPU DIAGNOSTICS
The processor performs diagnostics, or error checks, during its operation and sends status information to indicators that are normally located on the front of the CPU.
Typical diagnostics include memory OK, processor OK, battery OK, and power supply OK.
A watchdog timer is a mechanism of alert in case of failure.
This is a timer that gives alarm and may stop the PLC if its time is out. This timer is reset at each scan. the processor sends a pulse at the end of each scan indicating a correct system operation.
If a failure occurs, the processor does not send a pulse, the timer times out, and the a relay activates that can be used in an alarm circuit to signal a failure.

21. Thanks