1. DESIGN OF A GENERAL PURPOSE DIGITAL LOGIC TESTER AND ITS IMPLEMENTATION IN FPGA
Lopamudra Kundu
Reg. No. : of
Roll No.:- 91/RPE/060002
Koushik Basak
Reg. No. : of
Roll No.:- 91/RPE/060011

2. Hardware testing: Why & How ?
Verification of circuit functionality
Detection of faults, if any
Manufacturing fault
Stuck-at model
Manual testing using several techniques

3. Automation of Testing Circuit may be too large
Limitations of Manual Testing
Circuit may be too large
Number of circuits to be tested may be huge
Advantages of Automation Testing
High speed process
Reliable

4. Design Layout of Logic Tester
Device under test
Display

5. Block Diagram of Logic Tester

6. Software Aspect of Design
Tester
Memory (Stimulus & Response)
Device Under Test

7. Device Under Test 4-bit magnitude comparator
Compares two 4-bit numbers A and B
Gives three outputs corresponding to A>B, A=B & A<B
9’s complement of 4-bit number
Subtraction by addition
Each digit of a decimal number subtracted from 9 gives the 9’s complement of the number.

8. Flow Chart of Magnitude Comparator

9. Flow Chart of 9’s Complement

10. Simulation of DUT & Testing
Stimuli are fetched from the memory sequentially and input to DUT
Output of DUT is compared with the corresponding response stored in the memory
If they tally LED1 glows, otherwise LED2 glows

11. Hardware Aspect of Design
Field programmable gate array
Different components of FPGA
RS 232 serial port
Clock source
LED

12. Key Components of FPGA

13. Xilinx Spartan-3 Starter Kit Board

14. Algorithm of Hardware Tester Programmed in VHDL
Step 1: Store n = number of stimuli in array A
Step 2: Store n = number of responses in array B
Step 3: Down convert the system clock to 1Hz
Step 4: Assign i=1
Step 5: While i<=n Go to step End

15. Contd. Step 6: Arrival of a clock pulse Ai goes to the input of DUT
Step7: Clear C Store DUT output in C
Step8: Compare C and Bi
Step 9: Check (C=Bi)? a) Yes: X=1,Y= b) No: Y=1, X=0

16. Contd. Step 10: If X=1 Glow LED1 If Y=1 Glow LED2 Step 11: i=i+1
Step 12: Go to step 5

17. Results and Conclusions
DUT simulated by set of stimuli stored in the memory
Output compared with the stored response
If they tally LED1 glows
If they don’t tally LED2 glows

18. Further Scopes of Development
Test Vector Generation
MicroBlaze

19. Test Vector Generation
Reduction of number of stimuli required to test a DUT
Path sensitizing technique
Random test

20. MicroBlaze Architecture

21. Tester Using MicroBlaze

22. Thank You