1. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 0 Lesson 2 The Digital Logic Level

2. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 1 LESSON OVERVIEW  Revolution in electronics industry  Basic logic gates and Boolean Algebra  Combination of logic gates  Clocks  Memory chips  CPU chips and buses  Mulplexers

3. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 2 Logic Devices  Fixed Logic  Programmable Logic

4. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 3 Advantages of PLD Prototyping Method  With manual wiring reduced to minimum, prototypes can be constructed, tested, and modified at a much faster rate.  Wiring errors can be avoided.  You can experiment with many digital IC types without having to stock them in your supply cabinet.  Circuit designs can be saved as electronic files within the PC and used again when needed.  Since the PLD can be used over and over again, modifications can easily be made by altering the circuit in the PC, and then downloading the new design into the PLD.

5. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 4 Logic Gates Electronic circuits which combine digital signals according to the Boolean algebra are referred to as logic gates; because they control the flow of information. Positive logic is an electronic representation in which the true state is at a higher voltage, while negative logic has the true state at a lower voltage.

6. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 5 Three Basic Logic Gates  AND gate  OR gate  NOT gate

7. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 6 AND gate AND InputOutput ABAB 000 010 100 111

8. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 7 OR gate OR InputOutput ABA+B 000 011 101 111

9. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 8 NOT gate

10. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 9 NAND gate

11. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 10 NOR gate

12. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 11 EOR gate

13. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 12 ENOR gate

14. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 13

15. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 14

16. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 15 Basic Digital Logic Circuits  RTL : Resistor-Transistor Logic  DTL : Diode-Transistor Logic  TTL : Transistor-Transistor Logic  NMOS : N-channel Metal-Oxide Silicon  CMOS : Complementary Metal-Oxide Silicon  ECL : Emitter-Coupled Logic

17. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 16 Clock A clock is a circuit that emits a series of pulses or timing signals with a precise pulse width and precise time interval between pulses increasing time.

18. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 17 Period The time T for one complete cycle of the clock is known as the period.

19. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 18 Relation Between Frequency and Period It is common to characterize a clock in terms of its frequency where the frequency f is related to the period T by:

20. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 19 Memory Chips SIMMSingle-inline-memory-module DIMMDual-inline-memory-module

21. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 20 CPU Chips All modern CPUs are contained on a single (very large-scale integrated circuit) chip.

22. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 21 Types of Buses  Processor Bus  Memory Bus  I/O Bus

23. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 22 Processor Bus  is the communication pathway from the CPU and the system bus and possibly an external cache.  is to transfer data to and from the cache or system bus as fast as possible.  is running at a speed that is equal to the speed of the CPU.

24. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 23 Memory Bus  is used to transfer data between the CPU and main memory. is either the processor bus itself or another stand alone bus.  is much harder to judge the clock rate of the memory bus (if it is separate form processor bus).  is definitely not as fast as the processor bus.  is limited by the slowness of main memory.

25. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 24 I/O Bus  allows the computer to communicate with storage devices, modem printers, and other peripheral devices.  ISA  Micro Channel Architecture (MCA)  EISA  VESA Local Bus (VLB)  PCI  PCMCIA

26. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 25 Focus For Increased Performance Of The Bus  Faster CPUs  Increasing software demands  Greater video requirements

27. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 26 Multiplexers And Decoders_1 Multiplexers and decoders are used when many lines of information are being gated and passed from one part of a circuit to another. A decoder de-multiplexes the signals back onto several different lines.

28. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 27 Multiplexers And Decoders_2 Multiplexing Multiplexing is when multiple data signals share a common propagation path. Time multiplexing is when different signals travel along the same wire but at different times.

29. Computer Systems Architecture Copyright © Genetic Computer School 2008 SA 2- 28 Multiplexers And Decoders_3 These devices have data and addresses lines, and usually include enable/disable input. When the device is disabled the output is locked into some particular state and is not effected by the inputs.