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Introduction to Computer Design n Memory n Review of simple processor and memory n Fetch and execute cycle n Processor organization n Executing instructions.

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Presentation on theme: "Introduction to Computer Design n Memory n Review of simple processor and memory n Fetch and execute cycle n Processor organization n Executing instructions."— Presentation transcript:

1 Introduction to Computer Design n Memory n Review of simple processor and memory n Fetch and execute cycle n Processor organization n Executing instructions n Processor implementation Read MK 399-427, 449-464

2 6.2 - Jon Turner - 12/7/2015 Random Access Memory n Logically, a random access memory contains an array of numbered storage locations, called words. »when read/write is high, data_out is equal to the value stored in word specified by address inputs »when read/write is low, the value on data_in replaces the value in word specified by address outputs »separate enable signal also usually provided n Simplest RAMs are asynchronous - no clock input »synchronous circuits using RAMs must ensure that RAM timing requirements are satisfied to ensure correct operation data_in address read/write data_out... 0 1 2 3

3 6.3 - Jon Turner - 12/7/2015 Timing of RAM Operations n Read cycle » access time : time from “last” address change until output data is valid r/w data_in data valid t1t1 t2t2 t3t3 n Write cycle » t 1 is min time from address stable and enable asserted until r/w is lowered » t 2 is min time that input data must remain stable before r/w can be raised » t 3 is min time that address stays valid after r/w is raised » cycle time is t 1 + t 2 + t 3 address valid address enable Write cycle address valid address enable d_out data valid access time r/w Read cycle n Circuits using RAM must ensure timing conditions are met.

4 6.4 - Jon Turner - 12/7/2015 Implementing a RAM 4 word RAM with 4 bits per word address bits select row D C...

5 6.5 - Jon Turner - 12/7/2015 VHDL Model for SRAM entity lram16x64 is port ( reset, en, r_w: in STD_LOGIC; aBus: in STD_LOGIC_VECTOR(adrLength-1 downto 0); dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0)); end lram16x64; architecture arch of lram16x64 is type ram_typ is array(0 to memSize-1) of STD_LOGIC_VECTOR(wordSize-1 downto 0); signal ram: ram_typ; begin process(reset, en, r_w, aBus, dBus) begin if reset = '1' then ram(0) <= x"aaaa"; ram(1) <= x"5555"; elsif en = '1' and r_w = '0' then ram(conv_integer(unsigned(aBus))) <= dBus; end if; end process; dBus <= ram(conv_integer(unsigned(aBus))) when reset = '0' and en = '1' and r_w = '1' else (dbus’range => 'Z'); end arch; array of 16 bit words for memory initialize memory write to location specified by address bus read from location specified by address bus

6 6.6 - Jon Turner - 12/7/2015 Functional Simulation read cycles write cycles read cycles details of write

7 6.7 - Jon Turner - 12/7/2015 Timing Simulation Overview Read Cycle Detail Write Cycle Detail

8 6.8 - Jon Turner - 12/7/2015 Shrinking the Memory Cell n Computers and other digital systems generally use large amounts of memory. n Specialized memory cells have been developed to pack more memory in given amount of space. n Typical static RAM uses 6 transistor cell using pair of inverters and pair of pass transistors. n Bit line asserted to read or write the cell. n Complementary data lines used for input and output. n Column drivers enabled when writing. »large current capacity allows them to force cell to desired state data_in data_out SRAM cell column drivers sense amplifier bit line

9 6.9 - Jon Turner - 12/7/2015 Tri-State Buffers n A tri-state buffer has a data input and a control input. »when control input is asserted, output equals input »when control input is not asserted, output is disconnected from input - called high impedance state data_in data_out control n Tri-state buffers, can be used to build “distributed”multiplexors. n Shared outputs are called buses. n Also allows single wire to be used as data input and output. D1 SEL1 D0.. OUT data_in CMOS implementation   control data_out

10 6.10 - Jon Turner - 12/7/2015 Data Transfer Using Buses n A bus is a shared set of wires used to transfer data among any of several sources/destinations. Register 1 Q D LD Register 2 Q D LD Register 3 Q D LD »enabling source to place data on the bus n Data transfers involve: »loading data into destination

11 6.11 - Jon Turner - 12/7/2015 Static RAM Array (4x4) data_in data_out row decoder address r/w’..........

12 6.12 - Jon Turner - 12/7/2015 Static RAM Array (8x2).. data_in data_out row decoder address r/w ’.................... column decoder/demux column decoder/mux

13 6.13 - Jon Turner - 12/7/2015 Building Larger RAMs n Systems often require larger RAMs than can be constructed using a single SRAM component. n The use of an external decoder and the enable input allows larger RAMs to be constructed. n Alternative design uses 64Kx4 RAM chips. »no external decoder needed in this case SRAM 16Kx16 data address 2424 read/write ’ ENADDRDATA R/W ’ ENADDRDATA R/W ’ ENADDRDATA R/W ’ ENADDRDATA R/W ’ 64Kx16 RAM

14 6.14 - Jon Turner - 12/7/2015 Dynamic RAMs »each storage cell consists of a pass transistor and a capacitor » reading contents, destroys value –need to write back after reading »stored charge leaks from capacitor after 10-100 ms –requires periodic refresh of memory contents n DRAM cells are organized in 2D arrays, much like those for SRAM. »single data line rather than pair »requires sensitive sense amplifiers to detect stored charge »takes more time (10x) to read values than with SRAM select data storage capacitor n Dynamic RAMs use a simpler memory cell to enable more bits to be stored in a single chip (4-8x).

15 6.15 - Jon Turner - 12/7/2015 Addressing in Dynamic RAMs n Large memory chips require lots of address pins. n Many DRAM chips reduce number of address pins by dividing address into two parts. » row address determines which row in 2D array is selected » column address selects one or more bits in the row n Column address can be provided after row address without slowing down memory access. »so, same address pins can be used to supply both row and column addresses » Row Address Strobe (RAS), Column Address Strobe (CAS) used to load row and column addresses into on-chip registers n Refresh circuitry periodically reads each row in memory array and writes it back - often built into chip.

16 6.16 - Jon Turner - 12/7/2015 Basic Processor & Memory n Memory stores programs and data. »organized as set of numbered storage slots »each memory word can hold a number »processor can read from or write to any word n Fetch & execute cycle »read word whose address is in Program Counter (PC) and increment PC »interpret stored value as instruction (decoding) »perform instruction using Accumulator (ACC) and Arithmetic & Logic Unit (ALU) Controller PC Data Bus Address Bus Memory 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000a ffff... IRIARACC read/write ALU

17 6.17 - Jon Turner - 12/7/2015 Instruction Set 0000halt - halt execution 0001negate - ACC :=  ACC 1xxximmediate load – if sign bit of xxx is 0 then ACC := 0xxx else ACC := fxxx 2xxxdirect load - ACC := M [ 0xxx ] 3xxxindirect load - ACC := M [ M [ 0xxx ]] 4xxxdirect store - M [ 0xxx ] := ACC 5xxxindirect store – M [ M [ 0xxx ]] := ACC 6xxxbranch - PC := 0xxx 7xxxbranch if zero - if ACC = 0 then PC := 0xxx 8xxxbranch if positive - if ACC > 0 then PC := 0xxx 9xxxbranch if negative - if ACC < 0 then PC := 0xxx axxxadd - ACC := ACC + M [ 0xxx ]

18 6.18 - Jon Turner - 12/7/2015 Sample Program n Add the values in locations 20-2f and write sum in 10. AddressInstructionComment 0000 (start)1000 (ACC := 0000)initialize sum 00014010 (M[0010] := ACC) 00021020 (ACC := 0020)initialize pointer 00034011 (M[0011] := ACC) 0004 (loop)1030 ( ACC := 0030) if pointer = 030, quit 00050001 (ACC := -ACC) 0006a011 (ACC :=ACC+M[0011]) 0007700f (if 0 goto 000f) 00083011 (M[M[0011]] := ACC) sum = sum + *pointer 0009a010 (ACC :=ACC+M[0010]) 000a4010 (M[0010] := ACC) 000b1001 (ACC := 0001)pointer = pointer + 1 000ca011 (ACC :=ACC+M[0011]) 000d4011 (M[011] := ACC) 000e6004 (goto 0004)goto loop 000f (end)0000 (halt)halt 0010Store sum here 0011Pointer to next value

19 6.19 - Jon Turner - 12/7/2015 Execution of a Computer Program reset period execute first instruction - mload fetch first instruction fetch second instruction execute second instruction – dload

20 6.20 - Jon Turner - 12/7/2015 Detailed Processor Diagram IREG decode LD Addr Bus Data Bus statetick Control Logic (combinational circuit) mem_en mem_rw ACCALU compare LD OP IAR LD PC LD +

21 6.21 - Jon Turner - 12/7/2015 Processing Cycle n Instruction fetch » PC used to read word from memory » PC is incremented n Instruction decode »first 4 bits of retrieved instruction are decoded to determine what to do »appropriate circuitry activated n Instruction execution »retrieve additional memory words »write to memory »modify PC or ACC contents »may take different amounts of time to complete Fetch halt Negate mLoad dLoad dStore iStore Branch BrZero brPos brNeg Add iLoad

22 6.22 - Jon Turner - 12/7/2015 Instruction Execution n Direct Load »transfer data from memory to ACC, using low 12 bits of instruction word as memory address »requires asserting of memory signals and loading ACC n Conditional branch »determine if ACC =0 (or >0 or <0) »if so, transfer low 12 bits of instruction word to PC n Indirect store »transfer data from memory to Indirect Address Register ( IAR ) using low 12 bits of instruction word as memory address »transfer data from ACC to memory, using IAR contents as address »requires placing IAR value on address bus and asserting signals to perform memory write

23 6.23 - Jon Turner - 12/7/2015 IREG decode LD Addr Bus Data Bus statetick Control Logic (combinational circuit) mem_en mem_rw ACCALU compare LD OP IAR LD PC LD + Instruction Fetch 1. PC value on Abus 3. Load IREG 5. Increment PC 2. Memory contents on Dbus 1. mem_en := 1 4. mem_en := 0

24 6.24 - Jon Turner - 12/7/2015 IREG decode LD Addr Bus Data Bus statetick Control Logic (combinational circuit) mem_en mem_rw ACCALU compare LD OP IAR LD PC LD + Add Instruction Execution 1. mem_en := 1 2. Memory contents on Dbus 1. IREG value on Abus 4. Load sum into ACC 3. ALU adds values 5. mem_en := 0

25 6.25 - Jon Turner - 12/7/2015 Signal Timing for Processor NegatemLoadBranch enable memory for reading IREG loaded PC incremented ACC loaded PC loaded ACC loaded clk mem_en mem_rw pc ireg acc Fetch abus dbus pc ram add clk mem_en mem_rw pc ireg acc abus dbus ireg ram PC value on Abus

26 6.26 - Jon Turner - 12/7/2015 Signal Timing for Processor clk mem_en mem_rw abus dbus iar acc dLoad ireg ram clk mem_en mem_rw abus dbus iar acc iLoad ireg iar ram dStore clk mem_en mem_rw iar abus dbus acc ireg iStore clk mem_en mem_rw iar abus dbus ireg iar ram acc

27 6.27 - Jon Turner - 12/7/2015 entity cpu is port ( clk, reset:in std_logic; m_en, m_rw: out std_logic; aBus: out std_logic_vector(adrLength-1 downto 0); dBus: inout std_logic_vector(wordSize-1 downto 0)); end cpu; architecture cpuArch of cpu is type state_type is (reset_state,fetch,halt,negate,mload,dload,...); signal state: state_type; type tick_type is (t0, t1, t2, t3, t4, t5, t6, t7); signal tick: tick_type; signal pc: std_logic_vector(adrLength-1 downto 0); -- program counter signal iReg:std_logic_vector(wordSize-1 downto 0); -- instr. register signal iar: std_logic_vector(adrLength-1 downto 0); -- ind. addr. reg. signal acc: std_logic_vector(wordSize-1 downto 0); -- accumulator signal alu: std_logic_vector(wordSize-1 downto 0); -- alu output Processor VHDL Specification processor state and timing definitions primary processor registers

28 6.28 - Jon Turner - 12/7/2015 begin alu <= (not acc) + x"0001" when state = negate else acc + dbus when state = add else (alu'range => '0'); process(clk) -- perform actions that occur on rising clock edges function nextTick(tick: tick_type) return tick_type is begin case tick is when t0 => return t1; when t1 => return t2; when t2 => return t3; when t3 => return t4; when t4 => return t5; when t5 => return t6; when t6 => return t7; when others => return t0; end case; end function nextTick; procedure decode is begin case iReg(15 downto 12) is when x"0" => if iReg(11 downto 0) = x"000" then state <= halt; elsif iReg(11 downto 0) = x"001" then state <= negate; end if; when x"1" => state <= mload;... when x"a" => state <= add; when others => state <= halt; end case; end procedure decode; decode instructions ALU operations

29 6.29 - Jon Turner - 12/7/2015 procedure wrapup is begin state <= fetch; tick <= t0; end procedure wrapup; begin if clk'event and clk = '1' then if reset = '1' then state <= reset_state; tick <= t0; pc '0'); iReg '0'); acc '0'); iar '0'); else tick <= nextTick(tick) ; -- advance time by default case state is when reset_state => state <= fetch; tick <= t0; when fetch => if tick = t1 then iReg <= dBus; end if; if tick = t2 then decode; pc <= pc+'1'; tick <=t0; end if; when halt => tick <= t0; -- do nothing when negate => acc <= alu;wrapup; when mload => if iReg(11) = '0' then acc <= x"0" & ireg(11 downto 0); else acc <= x"f" & ireg(11 downto 0);end if; wrapup; load acc and fetch next sign extend for immediate load of negative values last step of every instruction

30 6.30 - Jon Turner - 12/7/2015 when dload => if tick = t1 then acc <= dBus; end if; if tick = t2 then wrapup; end if; when iload => if tick = t1 then iar <= dBus; end if; if tick = t4 then acc <= dBus; end if; if tick = t5 then wrapup; end if; when dstore => if tick = t4 then wrapup; end if; when istore => if tick = t1 then iar <= dBus; end if; if tick = t7 then wrapup; end if; when branch => pc <= x"0" & iReg(11 downto 0); wrapup; when brZero => if acc=x"0000" then pc <=x"0" & iReg(11 downto 0); end if; wrapup; when brPos => if acc(15) = '0' and acc /= x"0000" then pc <= x"0" & iReg(11 downto 0); end if; wrapup;... load IAR from memory load ACC from address specified by IAR

31 6.31 - Jon Turner - 12/7/2015 process(clk) begin -- perform actions for falling clock edges if clk'event and clk ='0' then if reset = '1' then m_en <= '0'; m_rw <= '1'; aBus '0'); dBus 'Z'); else case state is when fetch => if tick = t0 then m_en <= '1'; aBus <= pc; end if; if tick = t2 then m_en '0'); end if; when dload => if tick = t0 then m_en <= '1'; aBus <= x"0" & iReg(11 downto 0); end if; if tick = t2 then m_en '0'); end if; when iload => if tick = t0 then m_en <= '1'; aBus <= x"0" & iReg(11 downto 0); end if; synchronized to falling clock edge use PC to supply address use IREG to supply address

32 6.32 - Jon Turner - 12/7/2015 if tick = t2 then m_en '0'); end if; if tick = t3 then m_en <= '1'; aBus <= iar; end if; if tick = t5 then m_en '0'); end if; when dstore => if tick = t0 then m_en <= '1'; aBus <= x"0" & iReg(11 downto 0); end if; if tick = t1 then m_rw <= '0'; dBus <= acc; end if; if tick = t3 then m_rw <= '1'; end if; if tick = t4 then m_en <= '0'; aBus '0'); dBus 'Z'); end if;... end case; end if; end process; use IAR to supply address drop rw after address is stable raise rw before removing address

33 6.33 - Jon Turner - 12/7/2015 Processor Test Program ram(0) <= x"1a0f"; -- immediate load ram(1) <= x"2010"; -- direct load ram(2) <= x"3030"; -- indirect load ram(3) <= x"4034"; -- direct store ram(4) <= x"0001"; -- negate ram(5) <= x"2034"; -- direct load ram(6) <= x"0001"; -- negate ram(7) <= x"5032"; -- indirect store ram(8) <= x"0001"; -- negate ram(9) <= x"1fff"; -- immediate load ram(10) <= x"a008"; -- add ram(11) <= x"700d"; -- brZero ram(12) <= x"0000"; -- halt ram(13) <= x"1400"; -- immediate load ram(14) <= x"8010"; -- brPos ram(15) <= x"0000"; -- halt ram(16) <= x"0001"; -- negate ram(17) <= x"9013"; -- brNeg ram(18) <= x"0000"; -- halt ram(19) <= x"6015"; -- branch ram(20) <= x"0000";-- halt ram(21) <= x"8014"; -- brPos ram(22) <= x"7014"; -- brZero ram(23) <= x"0001"; -- negate ram(24) <= x"9014"; -- brNeg ram(25) <= x"0000"; -- halt ram(48) <= x"0031"; -- pointer for iload ram(49) <= x"5af0"; -- target of iload ram(50) <= x"0033"; -- pointer for istore ram(51) <= x"0000"; -- target of istore ram(52) <= x"f5af"; -- target of dstore

34 6.34 - Jon Turner - 12/7/2015 Processor Simulation

35 6.35 - Jon Turner - 12/7/2015 Processor Simulation fetch mLoad fetch dLoad fetch

36 6.36 - Jon Turner - 12/7/2015 Processor Simulation

37 6.37 - Jon Turner - 12/7/2015 Processor Simulation fetch iload dstore fetch

38 6.38 - Jon Turner - 12/7/2015 Processor Timing Simulation add instruction ACC =  1 initially adding 1 memory delay addition delay FF prop. plus chip IO delay

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