1. Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development Summary M. Noy 29-01-2003

2. M. Noy 29-01-2003 Some known (and relevant) signal FF1 (real) FF1 emulator (SW) SW comparison of processed data Analysis of functionality (later  pass/fail) Software Control Data processing Testing idea

3. M. Noy 29-01-2003 System status

4. M. Noy 29-01-2003 DAC V ocm VME interface for PC control digital sequencer 40MHz 12 bit DAC and fully differential op-amp with common mode offset analogue opto-tx 010010

5. M. Noy 29-01-2003 VME interface logic  Analogue section  Sequence control logic Sequence storage DAC Amplification+cm Analogue opto-tx

6. M. Noy 29-01-2003 Software I have developed software using XDAQ and the HAL FedTesterObject: encapsulates functionality  interface FedTesterApplication: instantiates a (the) FedTesterObject(s); inherits from xdaqApplication and FedTesterSOAPCommandListener Plus additional required SO class

7. M. Noy 29-01-2003 Results from the system: preliminary

8. M. Noy 29-01-2003 Analogue square wave, period 50ns. (channel 0, bias setting 0x17, gain setting 1) 10% to 90% rise time: 3.6  0.2 ns 90% to 10% fall time: 3.4  0.2 ns Settling time believed to be better than 17ns, analogue noise believed to be less than 10mV, but not characterised yet. The optical output is fed into the first Optobahn opto-rx version, through 50  co-ax, into a 50  terminated scope.

9. M. Noy 29-01-2003 Linearity looks sufficient, but no detailed measurements have been made yet.

10. M. Noy 29-01-2003 Muxed pair of APV25 frames with pedestals only. pedestals Error bits Header ticks

11. M. Noy 29-01-2003 Muxed pair of APV25 frames with a 1 MIP (approx.) hit

12. M. Noy 29-01-2003 HIP event: from the X5 beam test data. R. Bainbridge, M. Takahashi

13. M. Noy 29-01-2003 Development

14. VME Clock and trigger distribution (propagation matched lines) Master trigger in 4x6U VME cards Acting master M. Noy 29-01-2003 4 identical VME boards 6U in size

15. M. Noy 29-01-2003 Single Board 1 back end module controlling synchronisation and 4 front end modules Master triggers in Slave trigger and clock BE to FE bus with clock and L1A VME BE V2 Temp unit Front End Modules

16. SRAM - optional add on, 512kB x 36 @80MHz Front End Virtex 2 DAC x6Op-amp x6 3 channel analogue opto-tx 3 channel analogue opto-tx I2C from BE Serial connection from BE Clock and Trigger from BE Optical outputs To temp unit M. Noy 29-01-2003 Single Front End Module 6 DAC  6 op-amp  2 analogue opto-tx-hybrid (current layout)

17. M. Noy 29-01-2003 Summary The optical test board works, and will be used to test the FF1. Have a 9U crate, VME64x backplane, and 3.3v psu at IC. Software for the set up is functional, we can produce test vectors and sequence tests. Some work is required to make it more user-friendly. The next optical test card is being developed to provide multiple individually configurable channels, stepping towards more automation (  production testing)