1. 1 A High-Speed and Wide Detectable Frequency Range Phase Detector for DLLs Babazadeh, H.; Esmaili, A.; Hadidi, K.; NORCHIP, 2009 Digital Object Identifier: 10.1109/NORCHP.2009.5397812 Publication Year: 2009 NORCHIP, 2009 10.1109/NORCHP.2009.5397812 Student : ming-long chuang Date:03/29/2010 National Changhua University Department of Graduate Institute of Integrated Circuit Design

2. 2 Outline  Abstract  INTRODUCTION  PROPOSED PHASE DETECTOR  180° PHASE DIFFERENCE DETECTION  SIMULATION RESULTS  CONCLUSION

3. 3 Abstract  A very simple, low power, wide range and high accuracy Phase Detector (PD) is presented solving many problems of the conventional circuits.  SPICE simulation results show that the immune frequency range of operation is 1MHz to 2GHz.  The dead zone of the presented open loop PD is zero, makes it the best choice to be used in high speed DLLs.  This circuit is tested in 0.35um CMOS technology.

4. 4 INTRODUCTION  Many problems are encountered in generating clock signal in a high-speed system. Thus it is required for an on-chip clock generator. Both the PLLs and DLLs have been employed for the frequency synthesizers to generate the clock signal.  Phase Detector (PD) is the most important block of a DLL. Phase error is detected and applied to Charge Pump. So it is true to say that the accuracy of the PD determines the accuracy of the whole DLL.

5. 5 INTRODUCTION  As the phase difference critically affects the overall characteristic of the DLL, the PD should be designed to work accurately for many phase differences.  The first one called the dead-zone.  Secondly, some of the rising edges can be missed in the detection when the edges are overlapped with the reset signal internally generated in the PF, which is called missing edge problem.

6. INTRODUCTION  Conventional PFD

7. PROPOSED PHASE DETECTOR  The idea of a PD

8. 8 PROPOSED PHASE DETECTOR  Proposed PD

9. 9 PROPOSED PHASE DETECTOR  When inputs have very small phase difference, △ φ. Owing to finite rise time and fall time resulting from the capacitance seen at “lagcomp”, “UP” and “DN” nodes, the pulse may not find enough time to reach a logical level, failing to turn on the charge pump switches.  The range of - △ φ to + △ φ is called the dead zone of the PD. The importance of smaller dead zone is at the lock time. The larger the dead zone the more the lock time jitter.

10. 10 PROPOSED PHASE DETECTOR  Modified PD

11. 11 180° △ φ DETECTION  In most DLLs, there is also another detection circuits for generating “wrong lock detection” signal to prevent from locking at 2π phase difference, this signal is also applied to the charge pump and used to switch another current source (usually a greater one) for increasing or decreasing the charge pump output voltage and unlock the loop from wrong detection.  A similar detector circuit can be used along with the proposed PD to detect 180° phase difference.

12. 12 180° △ φ DETECTION  180° phase difference detection

13. 13 SIMULATION RESULTS  I/O characteristic of proposed PD at different frequencies

14. 14 SIMULATION RESULTS  The nonlinearity of the characteristic in high frequencies is not a problem since happens at large phase differences, where the polarity is more important than magnitude, and we see that the PD keeps the correct polarity.  This PD has a wide operating frequency range which can properly detect even phase difference of π/256 in whole operating frequency range.

15. 15 Conclusions  A very simple, low power, open loop and wide range Phase Detector is proposed which is suitable to use in DLLs.  Since this PD is an open loop one, it can detect very small phase differences in frequency range of 1MHz-2GHz with zero dead-zone and can be a good choice for DLL designers.

16. 16  Thank you for your attention