1. Rabi Mahapatra Department of Computer Science & Engineering Texas A&M University

2. Embedded Systems and Codesign Laboratory Lot of Cores on a BoardA Single Chip Many Core SoC have hundreds of IP cores on a single chip. Multi Core SoC have a handful of IP cores on a single chip.

3. Performance Demand is ever increasing Frequency is not increasing More transistors available on single die –50 billion transistors Soon! Embedded Systems and Codesign Laboratory

4. Power and Thermal Management Testing Operating System Design Modeling and Benchmarks Programming Model Memory Bandwidth Fault Tolerance Virtualization Support Embedded System and Codesign Laboratory

5. Embedded Systems and Codesign Laboratory Secure SoC Infrastructure HW Security Protocols Simulation Platform Test and Debug Software Support Benchmarks Test Infrastructure Reliability Aware Design Low Power Core Design Low Power Communication System Level Power Management Thermal Management Power & Energy Testing & Reliability SecurityDevelopment

6. Challenge #1

7. Embedded Systems and Codesign Laboratory Communication Accounts for Significant Power Application OS Level System Level Circuit Level 35% Various Levels of Power Management

8. As the number of cores per chip scales, on-chip busses will no longer meet performance needs Route packets not wires NoC Components –routers –core-network interfaces (CNI) –links Embedded Systems and Codesign Laboratory An Example NoC with Mesh Topology

9. What NoC Has to Offer? High Bandwidth Less sensitive to Wire Delay Versatile Infrastructure Scalable Communication Challenges Router Architecture? Power Management? Routing Algorithm Quality of Service Embedded Systems and Codesign Laboratory

10. Routers are primary component in NoC Buffers consume the most power in Router Embedded Systems and Codesign Laboratory Up to 79% Power Consumption Efficient Management of Buffer can save power

11. Reduce Active Buffers: Dynamic Buffer Management –Buffers are organized in blocks –Flows are monitored –Excess blocks are powered down based on traffic flow Use Energy Efficient Storage Encoding –SRAMs can be efficient buffer solution –Storing 0 ≠ Storing 1 –Encode the bits in packet to preserve energy Embedded Systems and Codesign Laboratory 20% Energy Savings can be achieved!

12. Dynamic Peak Power Budget Satisfaction Local Power Consumption is computed Neighbors Power is shared Non deterministic algorithm is used to calculate available budget Embedded Systems and Codesign Laboratory Calculate Local Power Estimate Share Exchange Information Update Power Budget 25% Performance Improvement

13. Intelligent Power budget Distribution Ant System inspired power budget distribution approach Power ants are sent from surplus region Beggar ants are sent from starving region Power is shared from surplus to starving region Embedded Systems and Codesign Laboratory Sink Source 20% Improvement in Power Budget Utilization Sharing Path

14. Pfair is an optimal scheduling algorithm for multiprocessor task scheduling Integrated DVFS (Dynamic voltage and frequency scaling) into the Pfair scheduling algorithm Feedback controller based allocation of additional job copies to manage reliability. Embedded Systems and Codesign Laboratory Task set DVS enabled Pfair Scheduler Feedback control Observed Reliability Additional job copies Reduced Failure rate compared to Pfair Up to 50% savings in energy

15. Implemented the Pfair scheduling algorithm (for MPSoC) in hardware Transformed floating point computations to integer domain. Embedded Systems and Codesign Laboratory Exponential savings in Energy consumption compared to software based scheduler

16. Temperature aware energy management (TA-DVS) at run time using novel slack reclamation Embedded Systems and Codesign Laboratory MF-DVSTA-DVS Worst Case Energy Consumption Increase Limited to 4% 19% Lower Temperature Violation No Increase in Energy Consumption Low Energy Consumption High Temperature Violation Task set EDF Scheduler Feedback control Temperature Estimation Slack Temperature constrained slack

17. What We Addressed A Low Power Router Buffer Architecture Peak Power Management Heuristic Intelligent Dynamic Power Budget Distribution Reliability and Temperature aware task scheduling Other Research Challenges Novel flow control to reduce power consumption further Context/Application aware power management System wide power policy management Embedded Systems and Codesign Laboratory

18. Challenge #2

19. Challenges –Shrinking feature sizes –Power density and temperature Advantages –NoC can be used as test delivery platform –Redundancy Many Core SoC present us with challenges and advantages in achieving reliable computing Reduced operational lifetime: the “bathtub” curve is getting shallower and narrower Embedded Systems and Codesign Laboratory Enhanced testing is necessary to meet application reliability requirements Graceful degradation Adaptable architectures

20. Many Core SoC will contain: –Processing, Memory, and I/O IP –Infrastructure IP For Debug, Yield, and Testing (TI-IP) TI-IP provides reliability and availability –No longer necessary to take chip off-line to test –Allows for fast, high-coverage testing –Already being deployed in commercial automotive SoC (Freescale MPC564xL) Embedded Systems and Codesign Laboratory

21. TI-IP becomes limited by scalability for Many Core –Many TI-IPs distributed across the SoC Each SoC Tile can have TI-IP and Test Vectors –Test vectors can be optimally divided across SoC based on NoC topology –This solves the problem of testing deeply embedded cores Embedded Systems and Codesign Laboratory TI-IP composed of: Test Controller Test Vector Memory Test Vector Set 12345 5x5 2D-Torus Example

22. Experimental Analysis: –Observe time to test SoC with and without distributed TI-IP –Measured over a variety of SoC sizes for scalability –Test time independent of SoC size for distributed TI-IP Embedded Systems and Codesign Laboratory 85% reduction in test time 94% reduction in test time

23. What We Addressed TI-IP: On-Line Testing Test Vector Storage Test Scheduling Open Problems Life Time Reliability? Diagnosis & Recovery? Fault Resilience? Embedded Systems and Codesign Laboratory

24. Challenge #3

25. SoC Security Attack Modeling HW Security Solution Protocol Development Security IP Design Threat Response Mechanism Embedded Systems and Codesign Laboratory

26. Weakness in SoC –Heterogeneous system: IP from different vendors –Tradeoff between security and performance –Decrease visibility and control –Improved attack techniques Sample Attacks –Denial of Service (DoS) –Bandwidth reduction –Draining or Sleep Deprivation –Extraction of secret info –Hijacking of programmable components

27. Divide the system into secure and unsecure areas –Secure area (ASIC) –Unsecure area (FPGA etc) Secure Bus Design –Extend conventional arbitration using Trojan Detection and Access Control Security IP Based Solution –Transaction Monitoring –Sandboxing Embedded Systems and Codesign Laboratory

28. Central Security Core Dedicated communication channel for security protocol Secure agents at each Core Distributed Response protocol is necessary Embedded Systems and Codesign Laboratory

30. State of Art Bio Inspired Modeling of Threat Response Mechanism Security Monitor Core Core Level Anomaly Detector Open Problems Attack Model Development Security Infrastructure Development Protocol Design Design of Security Core/IP Embedded Systems and Codesign Laboratory

31. Challenge #4

32. Major road block in advent of many core SoC Need better platform simulator and debugger Rapid development cycle Suitable Benchmarks to effectively evaluate many core SoC Embedded Systems and Codesign Laboratory Design Space Exploration Performance Evaluation Test and Debug Benchmarking and Standardization

33. Full System SoC Simulation Platform Built using SystemC Generic and Extensible Embedded Systems and Codesign Laboratory

34. NoCBench System ModelComponents of NoCBench System Kernel –Provides scheduling –Task management Core Library –Processor cores –Memory core –Other IP Network On Chip –NoC backbone with routers and CNIs Embedded Systems and Codesign Laboratory

35. Configuration Parameters Network on Chip –Router Details –Topology –Injection Limit –Power Model System –Scheduler –Task Configurations –Core Types Reported Metrics Network –Throughput –Latency –Power Application –Execution Time –Cycles –Power Embedded Systems and Codesign Laboratory

36. VPNoC Scalable architecture 16-100 cores support Run applications using traces Suitable for data analysis accelerators Can meet performance, power, protocol and security analysis Challenges Slow when using large number of nodes Fast Model is essential Embedded Systems and Codesign Laboratory

37. Benchmarking is a Challenge –Application Benchmark –Communication Benchmark –Large optimization problems –Social media data analysis –Many other large data analytic problems What kind of setup –How future “many core SoC” will look like Embedded Systems and Codesign Laboratory

38. What We Have VPNoC SoC simulation Micro Kernel Simple Scheduler Basic core library Limited IPC What Do We Need More core support Thread Library Support Application Benchmarks Embedded Systems and Codesign Laboratory

40. Many Core SoC is the future Challenges –Performance & Power –Test, Reliability & Security –Benchmarking More Information –http://codesign.cs.tamu.edu/index.php/research/soc- and-nochttp://codesign.cs.tamu.edu/index.php/research/soc- and-noc –http://codesign.cs.tamu.edu/index.php/research/real- time-systemshttp://codesign.cs.tamu.edu/index.php/research/real- time-systems

41. Embedded Systems and Codesign Laboratory